Re: [isa-dev] Conditional Branches Clarification

149 views
Skip to first unread message

Bruce Hoult

unread,
Feb 23, 2022, 4:52:29 AM2/23/22
to Kishan Shah, RISC-V ISA Dev
The manual is correct.

"This is confusing to me because I would think a BLT instruction can be synthesized to a BGE instruction by reversing operands, but the manual says a BLT can synthesize to a BGT."

No. You can substitute BLT and BGE for each other by reversing the DESTINATIONS.  e.g.

max:
    BLT a0,a1,1f
    MV a0,a1
1: RET

max:
    BGE a0,a1,1f
    RET
1: MV a0,a1
    RET

If you exchange the operands in either of the above functions then they will calculate min instead of max.

Look at it this way .... exchanging operands does not affect whether or not the branch is taken if the operands are equal. BLT and BGT both should NOT branch if the operands are equal. "BLT a,b,..." and "BGE b,a,..." can't possibly do the same thing because the second one branches if a and b are equal but the first one does not.


On Wed, Feb 23, 2022 at 7:54 PM Kishan Shah <kish...@usc.edu> wrote:
Hope this is the correct location to ask this. I've been working on designing a risc-v processor as part of a course project and am looking for some clarification regarding conditional branches as they are specified in the RISC-V Instruction Set Manual. I'm specifically looking for more information regarding BLT, BLE, BGT, and BGE instructions. 

In chapter 24 of the manual, there are listings for a BLT and a BGE instruction. In section 2.5 of the manual, this note is given: "Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively".

This is confusing to me because I would think a BLT instruction can be synthesized to a BGE instruction by reversing operands, but the manual says a BLT can synthesize to a BGT. In addition, the two instructions in the listing, BLT and BGE would be equivalent if operands were reversed. Wouldn't it make the most sense to have either BLT and BGT, or BLE and BGE, with the direction being to go from BLT to BGE or BGT to BLE (and vice versa) by swapping operands? I don't see how we can have a BLT and a BGE instruction pair as those two would be equal with swapping operands, but it wouldn't be possible to get BLE or BGT from either instruction. 

Essentially, my understanding is that the BGE in the instruction listing in chapter 24 should really say BGT (as this is the op-code I see for a BLE instruction from the compiler). Not sure what I'm missing.

Any clarification on this would be much appreciated. Thanks

--
You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/ddc0d11a-bb1b-4957-82bc-c86bf7124084n%40groups.riscv.org.
Reply all
Reply to author
Forward
0 new messages