Error: unrecognized opcode `int SYSVEC'

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Prashant Raigar

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Nov 7, 2022, 8:22:06 AM11/7/22
to RISC-V ISA Dev
Hi I am new to riscv architechture can some help me why I am facing this error

Kinza Zaman

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Nov 7, 2022, 8:25:58 AM11/7/22
to Prashant Raigar, RISC-V ISA Dev
can you give more details about what's the error and what you're doing?

-Kinza 

On Mon, Nov 7, 2022, 6:22 PM Prashant Raigar <raigerp...@gmail.com> wrote:
Hi I am new to riscv architechture can some help me why I am facing this error

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Philipp Tomsich

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Nov 7, 2022, 8:32:07 AM11/7/22
to Prashant Raigar, RISC-V ISA Dev
Your assembler input contains the string "int SYSVEC" where assembler (this looks like an error message from gas) expects an opcode.
Might be as simple as a .c/.h file being passed to gas by accident…


On Mon, 7 Nov 2022 at 14:22, Prashant Raigar <raigerp...@gmail.com> wrote:
Hi I am new to riscv architechture can some help me why I am facing this error

Prashant Raigar

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Nov 7, 2022, 8:41:41 AM11/7/22
to RISC-V ISA Dev, philipp...@vrull.eu, RISC-V ISA Dev, Prashant Raigar
.sect .text; .sect .rom; .sect .data; .sect .bss
.global __echo, __notify, __send, __receive, __sendrec

#! See src/kernel/ipc.h for C definitions
SEND = 1
RECEIVE = 2
SENDREC = 3
NOTIFY = 4
ECHO = 8
SYSVEC = 33 #! trap to kernel

SRC_DST = 8 #! source/ destination process
ECHO_MESS = 8 #! echo doesn't have SRC_DST
MESSAGE = 12 #! message pointer

#!*========================================================================*
#! IPC assembly routines *
#!*========================================================================*
#! all message passing routines save ebp, but destroy eax and ecx.

.sect .text
XLEN = 8
__send:
    addi sp, sp, -3*XLEN
    sd s0, 1*XLEN(sp)
    lw    s0, sp              #s0 frame pointer
    sd x12, 1*XLEN(sp)
    lw    x10, SRC_DST(s0)    #! eax = dest-src
    lw    x12, MESSAGE(s0)    #! ebx = message pointer
    li    x13, SEND            #! _send(dest, ptr)
    ecall                   #software interrupt
    ld x0, 1*XLEN(sp)
    ld x12, 1*XLEN(sp)
    addi sp, sp, 3*XLEN
    ret

here's the code 

Tommy Murphy

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Nov 7, 2022, 8:42:35 AM11/7/22
to Philipp Tomsich, Prashant Raigar, RISC-V ISA Dev
I could be wrong, but `int SYSVEC` looks suspiciously like a x86 asm instruction to trap to the Linux kernel. Are you sure that you're not passing x86 assembly code to the RISC-V toolchain? As mentioned above, you really need to provide more details/info about what you're trying to do and what happens/goes wrong.

Tommy Murphy

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Nov 7, 2022, 8:55:38 AM11/7/22
to Prashant Raigar, RISC-V ISA Dev, philipp...@vrull.eu, RISC-V ISA Dev, Prashant Raigar
> here's the code 

And what exactly are you doing with it?
A makefile or build log/output would help.
What toolchain are you using and where did you get it?

Kinza Zaman

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Nov 7, 2022, 9:06:27 AM11/7/22
to Tommy Murphy, Prashant Raigar, RISC-V ISA Dev, philipp...@vrull.eu
Yeah, it looks like an assembler issue, so maybe you can provide the command to compile the test, and then we could speak more.

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Tommy Murphy

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Nov 7, 2022, 9:09:58 AM11/7/22
to Kinza Zaman, Prashant Raigar, RISC-V ISA Dev, philipp...@vrull.eu
As ever with these sorts of questions, a small, self-contained, reproducible test case would help save time, avoid guessing, and eliminate unnecessary traffic on the mailing list...
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