Exceptions

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Gorkem Nisanci

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Sep 27, 2020, 6:42:33 PM9/27/20

to RISC-V ISA Dev

I attached two tables that have list of interrupts and exceptions. I want to learn more about the situations that can cause these traps. Do they have definition ? For example, when user Software Interrupt occurs ? . Are they defined in detail by RISCV or we will define the cause and handling approach ? I am designing micro architecture of RV32I in Verilog with machine and user mode only.

Thank you so much

/Gorkem Nisanci

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Shiva

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Sep 28, 2020, 1:11:12 AM9/28/20

to RISC-V ISA Dev, gn...@nau.edu

Hi ,

Please go through the following links, may be helpful for you

https://stackoverflow.com/questions/58726942/risc-v-exceptions-vs-interrupts

https://ibex-core.readthedocs.io/en/latest/exception_interrupts.html

Also check Section 1.6 of the unprivileged RISC-V specification

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