Public review of Svadu Standard Extension

[Ved Shanbhogue]

Greetings!

We are delighted to announce the start of the public review period for
the following proposed Fast Track extension:
Hardware Updating of PTE A/D Bits (Svadu)

The 30-day review period begins today, August 29, and ends officially
on September 27 (inclusive).

This extension is part of the Privileged Specification.

The Svadu specification can be obtained as a PDF here:
https://github.com/riscv/riscv-svadu/releases/download/v1.0-rc1/riscv-svadu.pdf

This document was generated from the source available in the following
GitHub repository:
https://github.com/riscv/riscv-svadu

To respond to the public review, please either email comments to the
public RISC-V ISA-Dev mailing list at <isa...@groups.riscv.org> or add
issues to the Svadu GitHub repo: https://github.com/riscv/riscv-svadu/issues

We welcome all input and appreciate your time and effort in helping us
by reviewing the specification.

During the public review period, corrections, comments, and suggestions
will be gathered for review by the Privileged ISA Committee. Any minor
corrections and/or uncontroversial changes will be incorporated into the
specification. Any remaining issues or proposed changes will be addressed
in the public review summary report. If there are no issues that require
incompatible changes to the public review specification, the Privileged ISA
Committee will recommend the updated specifications be approved and
ratified by the RISC-V Technical Steering Committee and the RISC-V Board
of Directors.

Thanks to all the contributors for all their hard work.

Regards,
Ved Shanbhogue