On Thu, Jun 28, 2018 at 5:45 AM, Bruce Hoult <bruce...@sifive.com
> I'm curious which architecture you're thinking of that can set or clear an
> arbitrary bit in a 32 bit variable in a register with a 2-byte instruction.
> i386 and amd64 both use a 5-byte instruction
> Thumb2, ARM, and Aarch64 all use a 4-byte instruction
table 6.1, p68.
that's 1 instruction (damn important ones on an EC) oh! i am
guessing, gnanasekar, you meant "4,6, or 8 instructions" not "4,6 or 8
> On Wed, Jun 27, 2018 at 9:07 PM, Gnanasekar R <gnanase...@gmail.com
>> Thanks for the inputs. I do understand that setting/clearing can be done
>> with 4,6 or 8 bytes depending on the bit position. But my point is, it can
Samuel Falvo wrote:
> Many ARM MCUs, for example,
> provide the ability to directly set or clear bits in memory through
> specialized regions of the memory map.
RVV does something similar (which is really neat), you can configure
the vector CSRs all at once into the most common configurations by
writing to a single CSR... and then for anything out-of-the-ordinary
follow up with further (specific) writes to other CSRs (addresses).
however, samuel, these are generally for memory-mapped peripherals,
not for general-purpose use. i'd find it very strange if a virtual
(or real) memory page was re-mapped to 32 or 64 times its actual size
(into a bit-field) in *general-purpose* memory. aside from anything
it would require the memory-accessing side of the memory bus
architecture to have 5 or 6 extra bits, internally. still, it's a
neat idea, not to be totally ruled out.