HVIP and related registers usage

[Oleksii Kurochko]

Hello @everyone,

I would like to ask about the HVIP register and its usage.
In the specification, it is mentioned the following:
```
The standard portion (bits 15:0) of hvip is formatted as shown in
Figure 8.6. Bits VSEIP, VSTIP,
and VSSIP of hvip are writable. Setting VSEIP=3D1 in hvip asserts a VS-
level external interrupt;
setting VSTIP asserts a VS-level timer interrupt; and setting VSSIP
asserts a VS-level software
interrupt.
```
According to Figure 8.6, only bits 10, 6, and 2 can have non-zero
values. However, when I read the HVIP register in HS mode, I sometimes
see bits that are shown as zero in Figure 8.6 being set to 1. I can't

figure out why this is happening.

```
Registers hip and hie are HSXLEN-bit read/write registers that
supplement HS-level=E2=80=99s sip and
sie respectively. The hip register indicates pending VS-level and
hypervisor-specific interrupts,
while hie contains enable bits for the same interrupts.

```

It is mentioned here that SIE (does it mean HS's SIE?) and HIE are
always mutually exclusive. But it doesn't mention that it affects HVIP.

Am I missing something?

```
For each writable bit in sie, the corresponding bit shall be read-only
zero in both hip and hie.
Hence, the nonzero bits in sie and hie are always mutually exclusive,
and likewise for sip and
hip.
```
And here I would like to ask if my understanding is correct. HIP is
used to indicate pending hypervisor interrupts (and also VS interrupts,
so why is HVIP needed? Can't HIP be updated instead of HVIP?) when I am
in hypervisor mode, and SIP is used when in guest mode. (Or does the
document mean HS's SIP?)
Based on the last paragraph, it is mentioned that si{e,p}[i] =3D
~hi{e,p}[i] ( is SI{E,P} related to HS-mode? ). So how is it possible
to tell the guest that it has a timer interrupt? What I mean is, if I
set hvip[timer_interrupt_number]=3D1, it means
{vs}sie[timer_interrupt_number] will also be 1, which means that
hi{e,p}[timer_interrupt_number] =3D 0. Does this mean the timer interrupt
should stop working in the hypervisor? So it seems that before setting
hvip[timer], it is needed to check hip[timer]. Is my understanding

correct?

And one last question: what is the expected procedure/sequence to
save/restore the HVIP register and related registers during a context

switch of vCPUs?

Thanks in advance.

Best regards,

 Oleksii