Pre-amption in RISC-V PLIC

[Ahsan Ali]

Hi All,

Do RISC-V Architecture support Pre-amption? 

Pre-amptiom is: [Low priority interrupt (LPI) is being serviced and a new high priority interrupt (HPI) came, should the execution of LPI be paused and execution of HPI starts?]

Please guide according to single core as well as multi-core concept.

Thanks and Regards,

Ahsan

[Tommy Murphy]

I presume that you actually mean "pre-Emption"?

You should probably have a look at the work in progress CLIC specification.

https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

And maybe also look up the PLIC and CLINT interrupt mechanisms that are deployed in some existing RISC-V implementions.

https://www.reddit.com/r/FPGA/comments/taxggf/implementation_of_interrupts_in_hardware/ 

[Allen Baum]

The current CLINT cannot do that without a bit of state saving at the beginning of the low priority interrupt handler, 

and restoration at the end, with no interrupts being allowed while that state save/restore takes place.

(there is some nuance here, depending on which privilege level is service the LPI and HPI. If HPI is serviced by Mmode and LPI by Smode,

 then you don't need to do the save/restore)

OTherwise you can tolerate that amount of latency, you could argue that it can preempt, but I suspect that's not what you have in mind.

The new CLIC spec should enable what you are looking for.

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[Ahsan Ali]

Can we have support of that in our PLIC if we want to do at our own? Although it is against RISCV architecture.

[Palmer Dabbelt]

On Mon, 27 Feb 2023 01:29:03 PST (-0800), 2019...@gmail.com wrote:
> Can we have support of that in our PLIC if we want to do at our own?
> Although it is against RISCV architecture.

Generally in RISC-V land you can do whatever you want, the question is
just whether software is going to support it. That really depends on
the project, but at least for stuff like Linux and GCC there's a pretty
strong precedent that we support whatever's in the hardware. It'd
really depend on what things look like, but we have some way uglier
stuff that's supported so my guess is it'd be viable. It'd still be a
headache for everyone, though.

We'd really need to see the hardware/spec/code to know for sure, though.

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