We are delighted to announce the start of the public review period for the following proposed standard extensions to the RISC-V ISA:
Sdext - External debug extension
Sdtrig - Hardware trigger extension
The review period begins today, 2024-01-18, and ends on 2024-02-17 (inclusive).
These extensions are described in the PDF spec, which was generated from the source available in the GitHub repo.
To respond to the public review, please either email comments to the public isa...@groups.riscv.org mailing list or add issues and/or pull requests (PRs) to the riscv-debug-spec GitHub repo. We welcome all input and appreciate your time and effort in helping us by reviewing the specification.
During the public review period, corrections, comments, and suggestions, will be gathered for review by the Debug Task Group. Any minor corrections and/or uncontroversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the public review summary report. If there are no issues that require incompatible changes to the public review specification, the SOC Infrastructure (HC) will recommend the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the RISC-V Board of Directors.
Thanks to all the contributors for all their hard work.
Tim Newsome
Co-Chair, Debug Task Group