Re: [RISC-V tech-announce] Public review for Smctr/Ssctr ISA extensions

[Beeman Strong]

The public review period for Smctr/Ssctr has closed.  I received two requests for clarifications:

Issue #32 - Transfer records are added to the wrong end of the FIFO?

Issue #33 - WRPTR behavior in RASEMU

These clarifications were incorporated in PR #34, and can be found in the latest spec release:

https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc4

The TG will now seek required approvals for the Ratification Ready state.  Thanks to those who reviewed the spec.

On Tue, Jul 23, 2024 at 12:47 PM Beeman Strong via lists.riscv.org <beeman=rivosi...@lists.riscv.org> wrote:

We are delighted to announce the start of the public review period for the proposed Control Transfer Records (Smctr/Ssctr) standard extensions to the RISC-V ISA.

The review period begins today, July 23, 2024, and ends on August 22, 2024.

This extensions are part of the Privileged Specification.  The extensions are described in the PDF spec available at:

https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3

which was generated from the source available in the following GitHub repo:

https://github.com/riscv/riscv-control-transfer-records/

To respond to the public review, please either email comments to the public isa-dev mailing list or add issues and/or pull requests (PRs) to the GitHub repo. We welcome all input and appreciate your time and effort in helping us by reviewing the specification.

During the public review period, corrections, comments, and suggestions, will be gathered for review by the Smctr/Ssctr authors. Any minor corrections and/or uncontroversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the public review summary report. If there are no issues that require incompatible changes to the public review specification, the Privileged ISA Committee will recommend the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the RISC-V Board of Directors.

Thanks to all the contributors for all their hard work.

Beeman Strong
Chair, RISC-V Performance Analysis SIG

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