Clarification on misa csr

[Joseph Rahmeh]

Hi All,

 

The privileged architecture spec (version 1.11) indicates that the misa register is read-write (table 2.4).  But section 3.1.1 says that the XML field may be writable (which suggests that it may also be read-only).

The remaining bits are either WARL or WIRI which suggests that they may be implemented as read only.  Since all the bits may be implemented as read only then can the whole register be read-only?

 

Thanks,

 

Joe

[Christoph Hellwig]

The misa register should generally be read-only except for a RV64 CPU
that also supports a RV32 mode (or in the future RV128 + RV64/32).

[Andrew Waterman]

It’s up to the implementation which, if any, parts of misa are read-only.

--
You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org.
To post to this group, send email to isa...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/BY2PR0401MB106196D451FBADC71D3E400CFB100%40BY2PR0401MB1061.namprd04.prod.outlook.com.

[Stefan O'Rear]

On Tue, Jan 9, 2018 at 2:48 PM, Christoph Hellwig
<Christop...@wdc.com> wrote:
> The misa register should generally be read-only except for a RV64 CPU
> that also supports a RV32 mode (or in the future RV128 + RV64/32).

The lower 26 bits of misa are defined to allow an implementation to
enable and disable standard extensions at runtime; this serves
virtualization use-cases, and may also be needed for lazy context
saving the V extension (past discussions have been inconclusive).

-s