Ved Shanbhogue
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to Hiruna Vishwamith, RISC-V ISA Dev
On Sun, Jul 28, 2024 at 03:28:46AM -0700, Hiruna Vishwamith wrote:
>I have been studying the 'A' extension (atomic instructions) for the RISC-V
>specification. I have gone through the spec, but it's a little difficult to
>understand. Can someone explain what each instruction does and its use
>cases?[image: a_extention.png]
>
An atomic operation appears to the rest of the system to occur indivisibly,
i.e., from the perspective of other harts, the operation has no intermediate
states that can be observed. They either do not occur or occur at once.
The atomic memory operation (AMO) instructions perform the following
read-modify-write operations atomically:
Atomic {
address = X[rs1]
rs2_val = X[rs2]
loaded_value = Memory[address]
switch instruction {
AMOSWAP: Memory[address] = rs2_val
AMOADD : Memory[address] = loaded_value + rs2_val
AMOXOR : Memory[address] = loaded_value ^ rs2_val
AMOAND : Memory[address] = loaded_value & rs2_val
AMOOR : Memory[address] = loaded_value | rs2_val
AMOMIN : Memory[address] = min(loaded_value, rs2_val)
AMOMAX : Memory[address] = max(loaded_value, rs2_val)
AMOMINU: Memory[address] = unsigned_min(loaded_value, rs2_val)
AMOMAXU: Memory[address] = unsigned_max(loaded_value, rs2_val)
}
x[rd] = loaded_value
}
The instructions with .W suffix operate on a word (32-bit values) and those
with .D operate on a doubleword (64-bit values).
Atomic operations help implement algorithms that require synchronization
and concurrent access to shared data structures. Examples include:
- Lock-Free and Wait-Free Data Structures: Queues, stacks, linked lists.
- Synchronization Primitives: Mutexes, spinlocks, semaphores.
- Parallel Algorithms: Histograms, parallel reduction, reference counting.
- Graph Algorithms: Concurrent BFS/DFS, MST.
These instructions may be used to implement equivalent C++ atomic functions
such as std::atomic_exchange, std::atomic_fetch_add, and
std::atomic_fetch_and.
regards
ved