timeline for "PMP Enhancements for memory access and execution prevention on Machine mode"

[Kokolakis, Georgios]

Hello,

I would like to ask if there's any timeline for the proposal "PMP Enhancements for memory access and execution prevention on Machine mode" (https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.ab3kl2ch725u), to be inserted as an extension in the official document of RISC-V privileged architecture. 

Thank you,

Georgios Kokolakis

Georgios Kokolakis | Graduate Research Assistant & PhD Student 

COEUS Center | KACB 3203 

Georgia Institute of Technology | Atlanta, GA 

gkoko...@gatech.edu

[Greg Chadwick]

If you look here: https://riscv.org/technical/specifications/ there is a link to 'Recently ratified, but not yet integrated, extension specifications'. If you follow the link you will find 'Smepmp' is one of them, which is the proposal document you refer to.

So whilst it is not yet in vol 2. of the specification it is ratified architecture.

Cheers,

Greg

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[Kokolakis, Georgios]

Thank you for you answer.

Does the "recently ratified" mean that whoever makes a RISC-V microarchitecture that includes the privilege extension should include those ratified extension specifications or is it not mandatory until those extension specifications are integrated? 

If it is the latter, is there a timeline regarding the integration?

kind regards, 

Georgios Kokolakis

Georgios Kokolakis | Graduate Research Assistant & PhD Student 

COEUS Center | KACB 3203 

Georgia Institute of Technology | Atlanta, GA gkoko...@gatech.edu

---

From: Greg Chadwick <g...@lowrisc.org>
Sent: Thursday, January 26, 2023 4:58 AM
To: Kokolakis, Georgios <gkoko...@gatech.edu>
Cc: isa...@groups.riscv.org <isa...@groups.riscv.org>
Subject: Re: [isa-dev] timeline for "PMP Enhancements for memory access and execution prevention on Machine mode"

 

[Allen Baum]

This is a ratified *extension*, and that means it is official, regardless of whether it is currently integrated into the mainline spec documentation.

No one has to wait to add it to their core.

As it is an extension, it is optional,  like any other extension; it is not mandatory 

(though any extension could be required for some RISC-V defined profile). 

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/BLAPR07MB7731FEFBDFC938A1033FA98691CF9%40BLAPR07MB7731.namprd07.prod.outlook.com.