Linker editing for processor extensions (ISA spec/use)

20 views
Skip to first unread message

Kevin Cameron

unread,
Mar 17, 2026, 1:18:02 PMMar 17
to RISC-V ISA Dev
I have been working with Claude-Code on a link-editor for Linux, one of the things it does is replace function calls with ISA extensions or processor specific methods. Here's the project -


Claude wrote the code, and says -

 The problem: Adding custom instructions to RISC-V hardware is easy (CUSTOM_0-3 opcode spaces).
  Getting the compiler to emit them requires modifying GCC/LLVM — intrinsics, machine descriptions,
  scheduling. That's months of toolchain work per extension.

  The solution: Don't modify the compiler. Compile with stock GCC, then rewrite the binary:

  # Stock code, stock compiler
  riscv64-linux-gnu-gcc -O2 -o simulator simulator.c -lm

  # Profile to find what's hot
  ./ldx -p gate_and,gate_or,gate_xor -- ./simulator

  # Implement hot functions in FPGA, define the mapping
  cat sim4state_accel.json
  # {"gate_and": {"opcode":"custom_0", "funct7":0, ...}, ...}

  # Rewrite — 4-state gate evals become single-cycle custom instructions
  python3 riscv_rewrite.py -i simulator -o simulator.hw -m sim4state_accel.json

  # Run on RISC-V + FPGA
  ./simulator.hw

  Two examples ready to demo:
  1. Math accelerator — sin/cos/sqrt → CUSTOM_0 (4 patches in trajectory computation)
  2. 4-state logic — gate_and/gate_or/gate_xor → CUSTOM_0 (5 patches in simulator inner loop, 32  signals per instruction cycle)

  The FPGA prototyping loop is the key selling point — change the hardware, re-run the one-line rewrite command, measure. No recompilation. When the extension is proven, tape it out.

----
Kev.

L Peter Deutsch

unread,
Mar 17, 2026, 3:09:25 PMMar 17
to Kevin Cameron, isa...@groups.riscv.org
> rewrite the binary:

Reed Hastings' former (?) company, whose name I don't remember at the moment
but whose product IIRC was runtime memory access error detection based on
automatic insertion of check code in binary code, has (or at least had) a
patent on some types of editing of linkable binaries. I testified against
awarding this patent, based on work that I and others did at Berkeley and
published in 1971, and lost because Hastings was able to assert that it
wasn't similar enough. (I think the patent should never have been granted,
based also on obviousness and perhaps on published work on link-time
optimization done at the DEC Palo Alto research facility, but the USPTO
didn't agree with me.) So if you are planning to do anything that involves
editing linkable binaries, I encourage you to research the legal issues.

--

L Peter Deutsch :: Aladdin Enterprises :: Healdsburg, CA & Burnaby, BC
Reply all
Reply to author
Forward
0 new messages