I have been working with Claude-Code on a link-editor for Linux, one of the things it does is replace function calls with ISA extensions or processor specific methods. Here's the project -
Claude wrote the code, and says -
The problem: Adding custom instructions to RISC-V hardware is easy (CUSTOM_0-3 opcode spaces).
Getting the compiler to emit them requires modifying GCC/LLVM — intrinsics, machine descriptions,
scheduling. That's months of toolchain work per extension.
The solution: Don't modify the compiler. Compile with stock GCC, then rewrite the binary:
# Stock code, stock compiler
riscv64-linux-gnu-gcc -O2 -o simulator simulator.c -lm
# Profile to find what's hot
./ldx -p gate_and,gate_or,gate_xor -- ./simulator
# Implement hot functions in FPGA, define the mapping
cat sim4state_accel.json
# {"gate_and": {"opcode":"custom_0", "funct7":0, ...}, ...}
# Rewrite — 4-state gate evals become single-cycle custom instructions
python3 riscv_rewrite.py -i simulator -o simulator.hw -m sim4state_accel.json
# Run on RISC-V + FPGA
./simulator.hw
Two examples ready to demo:
1. Math accelerator — sin/cos/sqrt → CUSTOM_0 (4 patches in trajectory computation)
2. 4-state logic — gate_and/gate_or/gate_xor → CUSTOM_0 (5 patches in simulator inner loop, 32 signals per instruction cycle)
The FPGA prototyping loop is the key selling point — change the hardware, re-run the one-line rewrite command, measure. No recompilation. When the extension is proven, tape it out.
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Kev.