another intel "optimisation"

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Luke Kenneth Casson Leighton

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Jun 15, 2018, 3:03:02 AM6/15/18
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Jacob Lifshay

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Jun 15, 2018, 2:34:03 PM6/15/18
to Luke Kenneth Casson Leighton, RISC-V ISA Dev
I think Intel's problems are not caused by their optimizations, but by speculating past everything that they shouldn't.
Jacob Lifshay

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Brady O'Brien

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Jun 15, 2018, 2:47:07 PM6/15/18
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The privileged spec does support lazy context-switching for the FPU. See the FS and XS fields of mstatus.

Alex Elsayed

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Jun 15, 2018, 3:25:37 PM6/15/18
to Brady O'Brien, RISC-V ISA Dev
The problem here is not lazy switching; it's that a Spectre-style attack can leak information that is in disabled functional units and register files.

Disabling lazy switching is the kludgy, oversized hammer that is being used to work around the more fundamental brokenness.

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