On Mon, 05 Nov 2018 22:31:09 PST (-0800), bmen...@gmail.com
> Hi Palmer,
> On Tue, Nov 6, 2018 at 3:03 AM Palmer Dabbelt <pal...@sifive.com
>> My understanding is that MPRV will handle this. Here's the text from the spec
>> Memory Privilege in mstatus Register
>> The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute
>> in all privilege modes. When MPRV=0, translation and protection behave as normal. When
>> MPRV=1, load and store memory addresses are translated and protected as though the current
>> privilege mode were set to MPP. Instruction address-translation and protection are unaffected.
>> MPRV is hardwired to 0 if U-mode is not supported.
>> So I think all you need to do is set MPP and MPRV to get machine-mode accesses
>> to behave like supervisor-mode accesses. At that point you can set up the page
>> tables such that you can access whatever memory you want.
> Thanks for the hints! However the spec does not explicitly mention
> page table can be altered in such configuration. It only indicates
> load/store memory will be translated to S-mode access which will go
> through MMU. If as you say we can set up new page tables to access
>>4GB memory in M-mode, I believe 'sfence.vma' is needed when modifying
> the SATP register. But again the spec does not mention such
> explicitly. In the spec 'sfence.vma' chapter indicates the instruction
> is for S-mode, but it does not provide any indication on if MPRV is to
> be used or not. Should such be clarified?
supervisor mode. So "sfence.vma" is valid from machine mode, and has the same