L Peter Deutsch
unread,Mar 25, 2024, 11:56:24 PMMar 25Sign in to reply to author
Sign in to forward
You do not have permission to delete messages in this group
Either email addresses are anonymous for this group or you need the view member email addresses permission to view the original message
to RISC-V ISA Dev
I found the new Jira interface, which I just used for the first time,
complex, confusing, and awkward; I had to click through something like 5
links just to get to the spec proposal. Is there a good resource somewhere
for learning how to navigate the new interface?
Meanwhile, Chapter 2 of the Zilsp draft says:
Regardless of endianness, the lower-numbered register holds the
low-order bits, and the higher-numbered register holds the
high-order bits: e.g., bits 31:0 of an operand in Zilsp might be
held in register x14, with bits 63:32 of that operand held in x15.
Consider the instruction ld rd,z. The above paragraph says that in a
big-endian system, the 32 bits at z..z+3 will be loaded into rd+1, and the
32 bits at z+4..z+7 will be loaded into rd, while in a LE system, z..z+3
will go to rd, and z+4..z+7 will go to rd+1. This is a reasonable choice
for actual 64-bit operands, but if a compiler wants to use these
instructions to (for example) reduce the number of instructions for storing
32-bit arguments onto the stack in a procedure prologue, it will have to be
aware of the fact that the two 32-bit values will be loaded and stored in
the opposite order depending on the system endianness: it will have to care
because the 32-bit values will be accessed individually from memory. I
think some version of this observation might be worth including in the spec.
--
L Peter Deutsch :: Aladdin Enterprises :: Healdsburg, CA & Burnaby, BC