# RISC-V - Function like representation of Instructions

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### Jim Kenua

Apr 19, 2023, 9:05:40 AMApr 19
to RISC-V ISA Dev
Hello,

I am working on a function-like representation of the instructions, each time I had to do changes on a core I had to look into the ISA manuals and read quite a number of pages just to remember the actual functions done by each instruction.

If someone knows a source from where I can extract a similar form it would great if it could be shared.

Please let me know if the below functions are miss wrote or if someone is interested in helping to write these.

Thank you all!

#######
LUI -> IRF[rd] = {SignExt(imm),12'd0};
AUIPC -> IRF[rd] = PC + {SignExt(imm),12'd0};
#######

#######
JAL -> IRF[rd] = PC + 4; PC = (PC + {SignExt(imm),1'b0});
JALR -> IRF[rd] = PC + 4; PC = (IRF[rs1] + {SignExt(imm),1'b0});
#######

#######
BEQ -> if (Signed / Unsigned(IRF[rs1]) == Signed / Unsigned(IRF[rs2])) PC = (PC + {SignExt(imm),1'b0});
BNE -> if (Signed / Unsigned(IRF[rs1]) != Signed / Unsigned(IRF[rs2])) PC = (PC + {SignExt(imm),1'b0});
BLT -> if (Signed (IRF[rs1]) < Signed (IRF[rs2])) PC = (PC + {SignExt(imm),1'b0});
BGE -> if (Signed (IFR[rs1]) >= Signed (IRF[rs2])) PC = (PC + {SignExt(imm),1'b0});
BLTU -> if ( Unsigned(IRF[rs1]) < Unsigned(IRF[rs2])) PC = (PC + {SignExt(imm),1'b0});
BGEU -> if ( Unsigned(IRF[rs1]) >= Unsigned(IRF[rs2])) PC = (PC + {SignExt(imm),1'b0});
#######

#######
LB -> IRF[rd] = SignExt(MEM[IRF[rs1] + SignExt(imm)][ 7:0]) // 1 Byte
LBU -> IRF[rd] = ZeroExt(MEM[IRF[rs1] + SignExt(imm)][ 7:0]) // 1 Byte
LH -> IRF[rd] = SignExt(MEM[IRF[rs1] + SignExt(imm)][15:0]) // 2 Bytes
LHU -> IRF[rd] = ZeroExt(MEM[IRF[rs1] + SignExt(imm)][15:0]) // 2 Bytes
LW -> IRF[rd] = SignExt(MEM[IRF[rs1] + SignExt(imm)][31:0]) // 4 Bytes
LWU -> IRF[rd] = ZeroExt(MEM[IRF[rs1] + SignExt(imm)][31:0]) // 4 Bytes
LD -> IRF[rd] = (MEM[IRF[rs1] + SignExt(imm)][63:0]) // 8 Bytes
#######

#######
SB -> MEM[IRF[rs1] + SignExt(imm)] = IRF[rs2][ 7:0]; // 1 Byte
SH -> MEM[IRF[rs1] + SignExt(imm)] = IRF[rs2][15:0]; // 2 Bytes
SW -> MEM[IRF[rs1] + SignExt(imm)] = IRF[rs2][31:0]; // 4 Bytes
SD -> MEM[IRF[rs1] + SignExt(imm)] = IRF[rs2][63:0]; // 8 Bytes
#######

#######
SLTI -> IRF[rd] = ZeroExt( Signed(IRF[rs1]) < Signed(SignExt(imm)));
SLTIU -> IRF[rd] = ZeroExt(Unsigned(IRF[rs1]) < Unsigned(SignExt(imm)));

SLT -> IRF[rd] = ZeroExt( Signed(IRF[rs1]) < Signed(IRF[rs2]));
SLTU -> IRF[rd] = ZeroExt(Unsigned(IRF[rs1]) < Unsigned(IRF[rs2]));
#######

#######
SLLIW -> IRF[rd] = SignExt((IRF[rs1] << imm[4:0])[31:0]);
SRLIW -> IRF[rd] = SignExt((IRF[rs1] >> imm[4:0])[31:0]);
SRAIW -> IRF[rd] = SignExt((IRF[rs1] >>> imm[4:0])[31:0]);
SLLI -> IRF[rd] = IRF[rs1] << imm[5:0];
SRLI -> IRF[rd] = IRF[rs1] >> imm[5:0];
SRAI -> IRF[rd] = IRF[rs1] >>> imm[5:0];

SLLW -> IRF[rd] = SignExt((IRF[rs1] << IRF[rs2][5:0])[31:0]);
SRLW -> IRF[rd] = SignExt((IRF[rs1] >> IRF[rs2][5:0])[31:0]);
SRAW -> IRF[rd] = SignExt((IRF[rs1] >>> IRF[rs2][5:0])[31:0]);
SLL -> IRF[rd] = IRF[rs1] << IRF[rs2][5:0];
SRL -> IRF[rd] = IRF[rs1] >> IRF[rs2][5:0];
SRA -> IRF[rd] = IRF[rs1] >>> IRF[rs2][5:0];
#######

#######
ADDI -> IRF[rd] = IRF[rs1] + SignExt(imm);
XORI -> IRF[rd] = IRF[rs1] XOR SignExt(imm);
ORI -> IRF[rd] = IRF[rs1] OR SignExt(imm);
ANDI -> IRF[rd] = IRF[rs1] AND SignExt(imm);
#######

#######
ADDW -> IRF[rd] = SignExt((IRF[rs1] + IRF[rs2])[31:0]);
SUBW -> IRF[rd] = SignExt((IRF[rs1] - IRF[rs2])[31:0]);

ADD -> IRF[rd] = IRF[rs1] + IRF[rs2];
SUB -> IRF[rd] = IRF[rs1] - IRF[rs2];
XOR -> IRF[rd] = IRF[rs1] XOR IRF[rs2];
OR -> IRF[rd] = IRF[rs1] OR IRF[rs2];
AND -> IRF[rd] = IRF[rs1] AND IRF[rs2];
#######

#######
MULW -> IRF[rd] = SignExt((Signed(IRF[rs1][31:0]) * Signed(IRF[rs2][31:0]))[31:0]);

MUL -> IRF[rd] = ( Signed(IRF[rs1]) * Signed(IRF[rs2]))[ XLEN -1:0 ];

MULH -> IRF[rd] = ( Signed(IRF[rs1]) * Signed(IRF[rs2]))[(XLEN*2)-1:XLEN];
MULHU -> IRF[rd] = (Unsigned(IRF[rs1]) * Unsigned(IRF[rs2]))[(XLEN*2)-1:XLEN];
MULHSU -> IRF[rd] = ( Signed(IRF[rs1]) * Unsigned(IRF[rs2]))[(XLEN*2)-1:XLEN];
#######

#######
DIV -> if (IRF[rs1] == -2**63 & IRF[rs2] == -1) IRF[rd] = -2**63 ; else
if (IRF[rs2] == 0 ) IRF[rd] = -1 ; else
IRF[rd] = Signed(IRF[rs1]) / Signed(IRF[rs2]); // Round towards Zero

DIVW -> if (IRF[rs1] == -2**31 & IRF[rs2] == -1) IRF[rd] = -2**31 ; else
if (IRF[rs2] == 0 ) IRF[rd] = -1 ; else
IRF[rd] = SigneExt(Signed(IRF[rs1][31:0]) / Signed(IRF[rs2][31:0])); // Round towards Zero

DIVU -> if (IRF[rs2] == 0) IRF[rd] = (2**64)-1 ; else
IRF[rd] = Unsigned(IRF[rs1]) / Unsigned(IRF[rs2]); // Round towards Zero

DIVUW -> if (IRF[rs2] == 0) IRF[rd] = (2**32)-1 ; else
IRF[rd] = SigneExt(Unsigned(IRF[rs1][31:0]) / Unsigned(IRF[rs2][31:0])); // Round towards Zero
#######

#######
REM -> if (IRF[rs1] == -2**31 & IRF[rs2] == -1) IRF[rd] = 0 ; else
if (IRF[rs2] == 0 ) IRF[rd] = IRF[rs1] ; else
IRF[rd] = Signed(IRF[rs1] % IRF[rs2]); // Sign of the result is equal to the dividend (rs1)

REMW -> if (IRF[rs1] == -2**31 & IRF[rs2] == -1) IRF[rd] = 0 ; else
if (IRF[rs2] == 0 ) IRF[rd] = IRF[rs1] ; else
IRF[rd] = SigneExt(Signed(IRF[rs1][31:0]) % Signed(IRF[rs2][31:0]));

REMU -> if (IRF[rs2] == 0) IRF[rd] = IRF[rs1] ; else
IRF[rd] = Unsigned(IRF[rs1]) % Unsigned(IRF[rs2]);

REMUW -> if (IRF[rs2] == 0) IRF[rd] = IRF[rs1] ; else
IRF[rd] = SigneExt(Unsigned(IRF[rs1][31:0]) % Unsigned(IRF[rs2][31:0]));
#######

####### CSR read accesses are classified as device input (I), and CSR write accesses are classified as device output (O).
CSRRW -> CSR_FILE[csr] = IRF[rs1] ; if (rd != 0) IRF[rd] = ZeroExt(CSR_FILE[csr]);
CSRRWI -> CSR_FILE[csr] = ZeroExt(uimm); if (rd != 0) IRF[rd] = ZeroExt(CSR_FILE[csr]);

CSRRS -> if (rs1 != 0) CSR_FILE[csr] = IRF[rs1] | CSR_FILE[csr]; IRF[rd] = ZeroExt(CSR_FILE[csr]);
CSRRSI -> if (uimm != 0) CSR_FILE[csr] = ZeroExt( uimm) | CSR_FILE[csr]; IRF[rd] = ZeroExt(CSR_FILE[csr]);

CSRRC -> if (rs1 != 0) CSR_FILE[csr] = ~IRF[rs1] & CSR_FILE[csr]; IRF[rd] = ZeroExt(CSR_FILE[csr]);
CSRRCI -> if (uimm != 0) CSR_FILE[csr] = ZeroExt(~uimm) & CSR_FILE[csr]; IRF[rd] = ZeroExt(CSR_FILE[csr]);
#######

### Tommy Murphy

Apr 19, 2023, 9:18:47 AMApr 19
to Jim Kenua, RISC-V ISA Dev
What about GCC's machine description files?

For example:

From: Jim Kenua <jimk...@gmail.com>
Sent: Wednesday, April 19, 2023 2:05:40 PM
To: RISC-V ISA Dev <isa...@groups.riscv.org>
Subject: [isa-dev] RISC-V - Function like representation of Instructions

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### Kito Cheng

Apr 19, 2023, 9:27:48 AMApr 19
to Tommy Murphy, Jim Kenua, RISC-V ISA Dev

### Rishiyur Nikhil

Apr 19, 2023, 10:09:51 AMApr 19
to Kito Cheng, Tommy Murphy, Jim Kenua, RISC-V ISA Dev
I second the recommendation and link in the previous message by Kito Cheng,
i.e., the Sail RISC-V ISA formal spec.
Nikhil