Public Review for 3 E-trace extensions (Standard Support Packet, Implicit Return and Data Trace of Multiple Memory Access and CAS)
Robertson, Iain
Greetings!
We are delighted to announce the commencement of the public review period for three extensions to the Efficient Trace for RISC-V 2.0 specification:
- Standard Support Packet
- Implicit Return
- Data trace of Multiple Memory Access and Compare and Swap
This 30-day review period begins today, 28-July-2026, and concludes on 27-Aug-2026.
The source for this document is available on GitHub: https://github.com/riscv-non-isa/riscv-trace-spec
The specification document is available for download as a PDF at the following link: https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.05-0.9/riscv-trace-spec-asciidoc.pdf
How to Provide Feedback:
To participate in the review, you may either:
- Reply to this thread on isa-dev (https://groups.google.com/a/groups.riscv.org/g/isa-dev), and/or
- Submit issues directly on the GitHub repository here: https://github.com/riscv-non-isa/riscv-trace-spec/issues
If you experience any difficulty accessing the document or GitHub links, please contact he...@riscv.org or the sender of this message directly. We will be happy to assist you or provide the document in an alternative format upon request.
Your Feedback Matters:
During the review period, we will gather corrections, comments, and suggestions for review by the SoC Horizontal Committee. Minor corrections and non-controversial changes will be directly incorporated. Any unresolved issues or significant proposed modifications
will be summarized in the public review report. Provided no major changes are required, the SoC Horizontal Committee
will recommend ratification by both the RISC-V
Technical Steering Committee and the
RISC-V
Board of Directors.
We greatly appreciate your contributions and feedback in refining this specification.
Warm regards,
Iain Robertson (Fast-track author, DTPM SIG chair)