RISC-V ISA: instruction timing

[Sajjad Tamimi]

HI

I need to find out what instruction is executing in each clock in RISC-V processor for my project. To this aim, I compiled and then executed MiBench benchmarks with Spike (spike -d) and extract the instruction’s execution flow. However, I still don’t know how many clock is needed for each instruction to operate. For example, multiplier and divider may consume 18 and 32 clocks, respectively.

I have searched a lot to find out that how many clock is needed for operation of each component or instruction in ISA RISC-V. but I couldn’t find any thing. 

I would really appreciate if you could help me with this issue.

Thanks in advance,

Yours sincerely

[Bruce Hoult]

Hi Sajjad,

There is no correct answer! RISC-V is not a CPU, it is a design for instructions to write programs for CPUs. Just like, for example, x86.

In the history of x86 there have been hundreds of different designs of CPUs made for it. Some have taken three clock cycles even for simple operations such as adding two registers together (8088/8086/80186) or as much as 15 clock cycles depending on the addressing mode used. The 8088 used up to 184 clock cycles to divide one 16 bit register by another, or 154 to multiply registers. These reduced, design by design, until Pentium was taking about 10 cycles for multiply and 40 for divide.

Now in Skylake, not only do mov or add take only 1 clock cycle, the CPU can do four of them in the same clock cycle! Multiplies now take three clock cycles, but you can start a new one every clock cycle. Divide still takes 20 or 30 clock cycles.

RISC-V will also eventually have many different implementations, with different speeds. It is not necessary for a RISC-V CPU to have multiply and divide instructions at all. They could exist but be slow. They could be fast. It depends on what the person who designs that chip needs.

As far as I know, only one RISC-V CPU is available for sale to the public right now, the SiFive-E310-G000. This is a 32 bit version of the Berkeley "Rocket" CPU. From the manual:

"The integer multiplier completes 8 bits per cycle, so takes up to four clock cycles for a single 32×32 multiply operation. The integer divider completes one bit per clock cycle, with an early out."

If you have $100k (actually, probably much less) then you could ask SiFive to make you some chips with different timings for multiply and divide. They could probably do it with a few months notice. From the SiFive E3 Coreplex manual:

"Two multiplier options are available: a fully pipelined multiplier with a two-cycle result latency, or an iterative multiplier of configurable latency. The iterative divider has a configurable latency of between three and 34 cycles and an early-out option."

That's the options for just one product from just one company. The same company will have another product, the E500 this year, and many other companies are also designing RISC-V CPUs.

The manuals I mentioned are available here:

https://dev.sifive.com/documentation/

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