RISC-V Implementation on Xillinx Nexus 4DDR

Jay

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Apr 4, 2018, 6:12:40 AM4/4/18

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Hello,

I am a Noob in RISC-V.

I am working with a school project and trying to implement RISC-V processor to my custom designed Xilinx Nexus 4DDR FPGA board.

My question is,

1. Is it possible to implement RISC-V processor to the board I am using?

3. Do you have any manuals about using RISC-V to FPGA?

4. Which tool do I have to use if I want to implement RISC-V to my board. And anny suggestion on software tools for C++ programming?

Richard W.M. Jones

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Apr 5, 2018, 2:58:20 PM4/5/18

to Jay, RISC-V ISA Dev

There's already a "port" to this board:

http://www.lowrisc.org/docs/ethernet-v0.5/

Rich.

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Jay

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Apr 10, 2018, 5:47:14 AM4/10/18

to RISC-V ISA Dev, jo...@hotmail.no

it it something similar out there with VHDL?

Guy Lemieux

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Apr 10, 2018, 9:05:36 AM4/10/18

to Jay, RISC-V ISA Dev

https://github.com/VectorBlox/orca

this is a pure vhdl implementation. sample systems for Xilinx ZedBoard and Altera DE2-115 are included.

you should be able to adapt the zedboard sample system to the nexus4. sometimes it helps to start with a working microblaze system, then replace it with orca — just be aware that this release of orca doesn’t have caches (still in testing; they’ll come soon).

guy

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Jay

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Apr 19, 2018, 4:49:15 AM4/19/18

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are you required to have linux to do the implementation?

Jay

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Apr 19, 2018, 4:49:56 AM4/19/18

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are you required to have Linux for the implementation ?

torsdag 5. april 2018 20.58.20 UTC+2 skrev Richard W.M. Jones følgende:

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