Implemetation of CSR (Machine Mode) as a beginner

[Abhav S Velidi.]

Hi all,

We have implemented the basic RV32I ISA, excluding the system calls. As beginners in this field we are finding it difficult to implement the privileged mode for the processor (in this case machine mode). We have gone through the privileged mode documentation and understood it. the problem we are facing is in how to implement these csr registers along with our regular RV32I core. Any documentation on how to go forward with implementing these registers alongside with the unprivileged core would be of great help.

Thanks in advanced

Regards
Abhav

[Tommy Murphy]

Maybe looking at some of the existing open-source RISC-V implementations might help?

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From: 'Abhav S Velidi.' via RISC-V ISA Dev <isa...@groups.riscv.org>
Sent: Monday, May 29, 2023 3:16:45 PM
To: RISC-V ISA Dev <isa...@groups.riscv.org>
Subject: [isa-dev] Implemetation of CSR (Machine Mode) as a beginner

 

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