Adding a Custom Instruction to RISC-V ISA

Justin Williams

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Mar 12, 2021, 7:34:35 PM3/12/21

to RISC-V ISA Dev

The ultimate goal here is to implement a custom instruction (multiply and accumulate for integers) on RISC-V ISA with the riscv-gnu-toolchain. I have extensively looked into the different articles and forums where people have inquired about this previously and came up with the following:

You can add the instruction to riscv-binutils (which is nice but not really what I am trying to accomplish).

You can add the instruction to GCC (if it is simple enough) by adding the instruction pattern to the machine description file (riscv.md).

I have tried adding my instruction to the riscv.md file and the compilation seems to be fine until it builds libc (this is a newlib build of riscv-gnu-toolchain by the way) where it fails.

What I added to riscv.md:

(define_insn "macsi4"

[(set (match_operand: SI 0 "register_operand" "=r")

(plus: SI (mult: SI (match_operand: SI 1 "register_operand" "r")

(match_operand: SI 2 "register_operand" "r"))

(match_operand: SI 3 "register_operand" "r")))]

"TARGET_MUL"

{ return TARGET_64BIT ? "macw\t%0, %1, %2, %3" : "mac\t%0, %1, %2, %3" ; }

[(set_attr "type" "arith")

(set_attr "mode" "SI")])

What is output when building riscv-gnu-toolchain fails:

riscv64-unknown-elf-ar rc ../libc.a

riscv64-unknown-elf-ar: ../stdlib/lib.a: No such file or directory

riscv64-unknown-elf-ar: ../search/lib.a: No such file or directory

riscv64-unknown-elf-ar: ../stdio/lib.a: No such file or directory

riscv64-unknown-elf-ar: ../time/lib.a: No such file or directory

riscv64-unknown-elf-ranlib libc.a

rm -rf tmp

So is there a tutorial or a series of steps you could give me to adding this instruction to RISCV-GCC?

Any response would be greatly appreciated.

-Justin

Jim Wilson

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Mar 12, 2021, 7:57:49 PM3/12/21

to Justin Williams, RISC-V ISA Dev

On Fri, Mar 12, 2021 at 4:34 PM Justin Williams <sleepdepriv...@gmail.com> wrote:

You can add the instruction to riscv-binutils (which is nice but not really what I am trying to accomplish).
You can add the instruction to GCC (if it is simple enough) by adding the instruction pattern to the machine description file (riscv.md).

If you don't add the instruction to binutils, then gcc will get an assembler error when it generates the instruction.

What is output when building riscv-gnu-toolchain fails:
riscv64-unknown-elf-ar rc ../libc.a
riscv64-unknown-elf-ar: ../stdlib/lib.a: No such file or directory
riscv64-unknown-elf-ar: ../search/lib.a: No such file or directory
riscv64-unknown-elf-ar: ../stdio/lib.a: No such file or directory
riscv64-unknown-elf-ar: ../time/lib.a: No such file or directory
riscv64-unknown-elf-ranlib libc.a

Keep in mind that the first error is the most useful one, and the last error is the least useful one. It looks like you are only showing the last error which provides no useful info.

Jim

Matt D.

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Mar 13, 2021, 7:22:28 AM3/13/21

to RISC-V ISA Dev, sleepdepriv...@gmail.com

On Saturday, March 13, 2021 at 1:34:35 AM UTC+1 sleepdepriv...@gmail.com wrote:

So is there a tutorial or a series of steps you could give me to adding this instruction to RISCV-GCC?

The following presentation may be of some help:

Porting the GNU CORE-V Toolchain
https://www.youtube.com/watch?v=RT0GqJySnBc
https://github.com/openhwgroup/corev-gcc
https://github.com/openhwgroup/corev-binutils-gdb
"In the first part of this presentation, we will discuss adding support for hardware loop instructions to GNU binutils. This has involved making changes to the GNU assembler, gas, and the GNU linker, ld. We will explain in technical detail how we ported this custom extension to binutils as well how we tested the resulting CORE-V assembler and linker.
The second part of this presentation will focus on adding hardware loops to GCC in three places; as built-in (intrinsic) functions, as code-generation patterns for the compiler and within target specific optimization. We shall give special attention to memcpy, the function to copy blocks of memory, and which GCC uses every time a struct is assigned or returned as a result."