Hello All,
We are delighted to announce the start of the public review period for RISC-V Platform-Level Interrupt Controller.
The review period begins today, September 2, 2022, and ends on October 16, 2022 (inclusive).
This Non-ISA specification is described in the PDF available at:
https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0_rc4
which was generated from the source available in the following GitHub repo:
https://github.com/riscv/riscv-plic-spec/
To respond to the public review, please either email comments to the public isa-dev mailing list or add issues and/or pull requests (PRs) to the GitHub repo. We welcome all input and appreciate your time and effort in helping us by reviewing the specification.
During the public review period, corrections, comments, and suggestions, will be gathered for review by the PLIC Task Group. Any minor corrections and/or uncontroversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the public review summary report. If there are no issues that require incompatible changes to the public review specification, the Privileged Software HC will recommend the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the RISC-V Board of Directors.
Thanks to all the contributors for all their hard work.
Aaron Durbin, on behalf of Abner Chang (renba...@gmail.com)
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On Fri, Sep 23, 2022 at 6:10 AM Ved Shanbhogue <v...@rivosinc.com> wrote:
> 2. Not needing to support partial read/write will have hardware simplifications
> by not needing read-modify-write. So if there is no useful case for needing
> such accesses from software usages it may be beneficial to not require it.
Using byte-enables, already available on the bus, allows for sub-word
accesses without read-modify-write cycles.
> 3. The specification is silent on the endianness of the registers. Was that
> planned to be specified in a later platform specification?
RISC-V is, in the absence of any other platform-specific feature,
understood to be little-endian. It seems reasonable that a PLIC
standard designed to work with RISC-V would also use little-endian
representation.
But, if subword addressing is not supported, it's irrelevant. As long
as bit N of a register aligns with bit N on the data bus, endianness
doesn't matter.
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Samuel A. Falvo II
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Using byte-enables, already available on the bus, allows for sub-word accesses without read-modify-write cycles.
IMO, I think the discussion has gotten a bit far afield of the original query. While some of things being discussed are interesting, I would still like to see the original point resolved. I believe the original question was whether PLIC implementations are required to support byte, halfword, and doubleword writes, and doublword reads. If the PLIC is being accessed only by RISC-V LW and SW instructions, then byte-write enables are not required in its implementation, and the ability to read 64-bit values are not required. If such a restriction were made, some implementations might choose to only support 32-bit read/write, which is presumably a simplification. Other PLICs might choose to support a wider variety of read/write sizes (e.g. if there were 16-bit microcontrollers present in the system doing smaller writes), but these days that seems less necessary.
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I'd say "accessed atomically with the LW and SW instructions", to avoid any confusion with the A atomic memory operations.On Sun, Sep 25, 2022, 11:49 PM Sean Halle <sean...@gmail.com> wrote:
Good discussion. In the end, we need concrete text.
Taking another stab at it:
"c
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