RV32E toolchain

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akhilesh Kotwaliwale

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Jan 13, 2023, 6:03:13 AM1/13/23
to RISC-V ISA Dev
Hi all,
I am trying to configure RV32E toolchain with picorv32 on my local system. But the linker is throwing an error while mapping as shown below.
Screenshot from 2023-01-13 15-41-18.png
Can anyone kindly help me finding bugs?
Thank you.

Tommy Murphy

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Jan 13, 2023, 7:01:16 AM1/13/23
to akhilesh Kotwaliwale, RISC-V ISA Dev
Where did you get that toolchain from?
At 8.2.0 it seems very old.
And it also looks like a bare metal toolchain but is being passed Linux toolchain flags and seems to be looking for glibc rather than newlib which is odd.
I would start by looking for a more recent toolchain.

martin ribelotta

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Jan 13, 2023, 7:13:44 AM1/13/23
to Tommy Murphy, akhilesh Kotwaliwale, RISC-V ISA Dev
Here: https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases
This bundles a multilib toolchain with rv32e support.

This is the result of execute riscv-none-elf-gcc -print-multi-lib:
rv32e/ilp32e;@march=rv32e@mabi=ilp32e
rv32ea/ilp32e;@march=rv32ea@mabi=ilp32e
rv32eac/ilp32e;@march=rv32eac@mabi=ilp32e
rv32ec/ilp32e;@march=rv32ec@mabi=ilp32e
rv32em/ilp32e;@march=rv32em@mabi=ilp32e
rv32ema/ilp32e;@march=rv32ema@mabi=ilp32e
rv32emac/ilp32e;@march=rv32emac@mabi=ilp32e
rv32emc/ilp32e;@march=rv32emc@mabi=ilp32e
rv32i/ilp32;@march=rv32i@mabi=ilp32
rv32ia/ilp32;@march=rv32ia@mabi=ilp32
rv32iac/ilp32;@march=rv32iac@mabi=ilp32
rv32iaf_zicsr/ilp32f;@march=rv32iaf_zicsr@mabi=ilp32f
rv32iafc_zicsr/ilp32f;@march=rv32iafc_zicsr@mabi=ilp32f
rv32iafd_zicsr/ilp32d;@march=rv32iafd_zicsr@mabi=ilp32d
rv32iafdc_zicsr/ilp32d;@march=rv32iafdc_zicsr@mabi=ilp32d
rv32ic/ilp32;@march=rv32ic@mabi=ilp32
rv32if_zicsr/ilp32f;@march=rv32if_zicsr@mabi=ilp32f
rv32ifc_zicsr/ilp32f;@march=rv32ifc_zicsr@mabi=ilp32f
rv32ifd_zicsr/ilp32d;@march=rv32ifd_zicsr@mabi=ilp32d
rv32ifdc_zicsr/ilp32d;@march=rv32ifdc_zicsr@mabi=ilp32d
rv32im/ilp32;@march=rv32im@mabi=ilp32
rv32ima/ilp32;@march=rv32ima@mabi=ilp32
rv32imaf_zicsr/ilp32f;@march=rv32imaf_zicsr@mabi=ilp32f
rv32imafc_zicsr/ilp32f;@march=rv32imafc_zicsr@mabi=ilp32f
rv32imafd_zicsr/ilp32d;@march=rv32imafd_zicsr@mabi=ilp32d
rv32imafdc_zicsr/ilp32d;@march=rv32imafdc_zicsr@mabi=ilp32d
rv32imc/ilp32;@march=rv32imc@mabi=ilp32
rv32imf_zicsr/ilp32f;@march=rv32imf_zicsr@mabi=ilp32f
rv32imfc_zicsr/ilp32f;@march=rv32imfc_zicsr@mabi=ilp32f
rv32imfd_zicsr/ilp32d;@march=rv32imfd_zicsr@mabi=ilp32d
rv32imfdc_zicsr/ilp32d;@march=rv32imfdc_zicsr@mabi=ilp32d
rv64i/lp64;@march=rv64i@mabi=lp64
rv64ia/lp64;@march=rv64ia@mabi=lp64
rv64iac/lp64;@march=rv64iac@mabi=lp64
rv64iaf_zicsr/lp64f;@march=rv64iaf_zicsr@mabi=lp64f
rv64iafc_zicsr/lp64f;@march=rv64iafc_zicsr@mabi=lp64f
rv64iafd_zicsr/lp64d;@march=rv64iafd_zicsr@mabi=lp64d
rv64iafdc_zicsr/lp64d;@march=rv64iafdc_zicsr@mabi=lp64d
rv64ic/lp64;@march=rv64ic@mabi=lp64
rv64if_zicsr/lp64f;@march=rv64if_zicsr@mabi=lp64f
rv64ifc_zicsr/lp64f;@march=rv64ifc_zicsr@mabi=lp64f
rv64ifd_zicsr/lp64d;@march=rv64ifd_zicsr@mabi=lp64d
rv64ifdc_zicsr/lp64d;@march=rv64ifdc_zicsr@mabi=lp64d
rv64im/lp64;@march=rv64im@mabi=lp64
rv64ima/lp64;@march=rv64ima@mabi=lp64
rv64imac/lp64;@march=rv64imac@mabi=lp64
rv64imaf_zicsr/lp64f;@march=rv64imaf_zicsr@mabi=lp64f
rv64imafc_zicsr/lp64f;@march=rv64imafc_zicsr@mabi=lp64f
rv64imafd_zicsr/lp64d;@march=rv64imafd_zicsr@mabi=lp64d
rv64imafdc_zicsr/lp64d;@march=rv64imafdc_zicsr@mabi=lp64d
rv64imc/lp64;@march=rv64imc@mabi=lp64
rv64imf_zicsr/lp64f;@march=rv64imf_zicsr@mabi=lp64f
rv64imfc_zicsr/lp64f;@march=rv64imfc_zicsr@mabi=lp64f
rv64imfd_zicsr/lp64d;@march=rv64imfd_zicsr@mabi=lp64d
rv64imfdc_zicsr/lp64d;@march=rv64imfdc_zicsr@mabi=lp64d


You can see the support of rv32emac and all of their variants (e, ec, emc, etc). The @march, @mabi indicate the combination of -march=... and -mabi=... in the command line that select the correct mode.


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Tommy Murphy

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Jan 13, 2023, 7:33:19 AM1/13/23
to martin ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
That link is to a toolchain that's much more recent than the one in your screenshot?
From: martin ribelotta <martinr...@gmail.com>
Sent: Friday, January 13, 2023 12:13:29 PM
To: Tommy Murphy <tommy_...@hotmail.com>
Cc: akhilesh Kotwaliwale <akhil...@gmail.com>; RISC-V ISA Dev <isa...@groups.riscv.org>
Subject: Re: [isa-dev] RV32E toolchain
 

martin ribelotta

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Jan 13, 2023, 8:59:22 AM1/13/23
to Tommy Murphy, akhilesh Kotwaliwale, RISC-V ISA Dev
Yes, that's it. The last version is gcc 12.2.0 but you have 11.x, 10.x and 8.x series

Tommy Murphy

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Jan 13, 2023, 9:57:40 AM1/13/23
to martin ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
@akhilesh Kotwaliwale - can you post (attach) a full build log to show what exactly is going on please?

Also - can you post logs rather than screenshots as they are very difficult to read on some devices and for some people.
Message has been deleted

akhilesh Kotwaliwale

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Jan 16, 2023, 3:39:47 AM1/16/23
to RISC-V ISA Dev, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev, Tommy Murphy
Hey,
I have followed your lead Martin Ribelotta, and it requires me to have glibc 2.28 for ubuntu 18.04.
While trying to do so, I got stuck and confused what the error is.
Attaching hereby the complte build log.
log

Tommy Murphy

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Jan 16, 2023, 4:44:01 AM1/16/23
to akhilesh Kotwaliwale, RISC-V ISA Dev, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
The latest xPack Project RISC-V toolchain doesn't require GLIBC v2.28:


What happens when you try that?

From: akhilesh Kotwaliwale <akhil...@gmail.com>
Sent: Monday, January 16, 2023 8:39:47 AM
To: RISC-V ISA Dev <isa...@groups.riscv.org>
Cc: Martin Ribelotta <martinr...@gmail.com>; akhilesh Kotwaliwale <akhil...@gmail.com>; RISC-V ISA Dev <isa...@groups.riscv.org>; Tommy Murphy <tommy_...@hotmail.com>

Subject: Re: [isa-dev] RV32E toolchain

akhilesh Kotwaliwale

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Jan 16, 2023, 4:51:00 AM1/16/23
to RISC-V ISA Dev, Tommy Murphy, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
I require it for installing xpm.

Tommy Murphy

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Jan 16, 2023, 4:54:55 AM1/16/23
to akhilesh Kotwaliwale, RISC-V ISA Dev, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
> I require it for installing xpm.

You don't need xpm.
Just download the toolchain archive and extract it.

akhilesh Kotwaliwale

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Jan 17, 2023, 12:22:09 AM1/17/23
to RISC-V ISA Dev, Tommy Murphy, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
Ok. I have done that. I guess the toolchain is built. But the error while running simulation.

vvp -N testbench.vvp
TRAP after 8224 clock cycles
ERROR!
Makefile:25: recipe for target 'test' failed
make: *** [test] Error 1

Tommy Murphy

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Jan 17, 2023, 2:27:48 AM1/17/23
to akhilesh Kotwaliwale, RISC-V ISA Dev, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
Sorry, I don't know what vvp is.
This, or something related?


It would help to provide more detailed context and details of what you're trying to run/simulate here.

Doesn't this vvp provide options to get more details - e.g. verbose log etc.?

Tommy Murphy

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Jan 17, 2023, 2:47:31 AM1/17/23
to akhilesh Kotwaliwale, RISC-V ISA Dev, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
Oh - is vvp here Icarus Verilog?
If so, then wouldn't the -v flag help?
And maybe some of the other diagnostic flags?

akhilesh Kotwaliwale

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Jan 17, 2023, 3:46:13 AM1/17/23
to RISC-V ISA Dev, Tommy Murphy, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
It is an error in verilog testbench. The variable test_passed is not receiving the value 1. I am now trying to debug.
testbench.v

Tommy Murphy

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Jan 17, 2023, 4:53:42 AM1/17/23
to akhilesh Kotwaliwale, RISC-V ISA Dev, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
Did you see this already?


"Note: The test bench is using Icarus Verilog. However, Icarus Verilog 0.9.7 (the latest release at the time of writing) has a few bugs that prevent the test bench from running. Upgrade to the latest github master of Icarus Verilog to run the test bench."

akhilesh Kotwaliwale

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Jan 17, 2023, 5:04:13 AM1/17/23
to RISC-V ISA Dev, Tommy Murphy, Martin Ribelotta, akhilesh Kotwaliwale, RISC-V ISA Dev
Yes i did. And I have icarus verilog version  10.1
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