Re: [RISC-V tech-announce] Public review of Svadu Standard Extension

[Ved Shanbhogue]

>The 30-day review period begins today, August 29, and ends officially
>on September 27 (inclusive).

The review is now concluded.

Feedback and resolution summarized:
Issue #15 [1]: "Purpose of ordering the A/D bit updates by a FENCE"
We created PR #18 [2] to add the following comment:
  "The PTE updates due to memory accesses ordered after
a FENCE are not themselves ordered by that FENCE."
  and to update the phrase "result of speculation" to:
  "result of speculation, even if the associated memory
   access is ultimately not performed architecturally."

Issue #20 [3]: "PTE-Update text can be misleading"
  We concluded that no change is required.

Issue #21 [4]: "ADUE should be under S-mode control"
  While a control toggleable at the S/VS level could
be a legitimate architectural option, we believe
the current approach of using the SBI offers similar
  functionality. Given the infrequent need to modify
this setting, the overhead introduced by an SBI call
is not a significant concern. Therefore, we don't
see a compelling reason to make a change at this
point.

Thanks for the contributions.

regards,
ved

[1] https://github.com/riscv/riscv-svadu/issues/15
[2] https://github.com/riscv/riscv-svadu/pull/18
[3] https://github.com/riscv/riscv-svadu/issues/20
[4] https://github.com/riscv/riscv-svadu/issues/21