RISC-V SoC for Xilinx FPGA

[Vereese Van Tonder]

Hi Everyone,

I am new to the RISC-V community, and very excited to get started on this tech.

I'd like to implement a RISC-V SoC for the Xilinx Virtex-7 FPGA. Can anyone suggest a starting point? Currently, I'm looking at the rocket-boom chip.

Any advice / pointers would be greatly appreciated.

--

Kind Regards,

Vereesé

[Palmer Dabbelt]

SiFive's Freedom repository contains build scripts that will generate a
bitstream for the VC707 evaluation kit, which contains a Virtex-7
XC7VX485T-2FFG1761C.

https://github.com/sifive/freedom

You should just be able to do something like "make -f Makefile.u500vc707devkit"
and get the bitstream out (assuming you've got all the relevant FPGA tools
working). We've had people reproduce this outside of SiFive multiple times, so
it should all work.

There are also targets for other FPGA development boards in the repo, and if
you're interested we'd love to have you contribute support for your board.

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