Clarification regarding NaN in fcvt instructions

[Bernhard Schommer]

Hi,

i have a question regarding the result of the fcvt.d.s and fcvt.s.d for any NaN argument. Since there is nothing additionally specified for the instruction in both cases is it the case that the canonical NaN is returned and the payload is zeroed?

Thanks,

-Bernhard

[Jim Wilson]

On Tue, Mar 22, 2022 at 9:08 AM Bernhard Schommer <bernhard...@gmail.com> wrote:

i have a question regarding the result of the fcvt.d.s and fcvt.s.d for any NaN argument. Since there is nothing additionally specified for the instruction in both cases is it the case that the canonical NaN is returned and the payload is zeroed?

One way to get answers to questions like this is to look at spike, which is (or at least used to be) the golden reference simulator for the ISA.  You can run a small testcase through spike, or you can look at the spike source code.  It does look like it handles fcvt same as all of the other F instructions.  You can find spike at github.com/riscv/riscv-isa-sim.

Jim

[Nick Knight]

My reading of the ISA manual is that the following statement from Sec. 13.3,

Except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical
NaN. The canonical NaN has a positive sign and all significand bits clear except the MSB, a.k.a.
the quiet bit.

continues to be in force in Sec. 14.5.

So yes, NaNs are canonicalized, which also implies quieting signalling NaNs. The requirement that NV is raised on an sNaN input for these instructions does not appear to be explicit in the ISA manual; it follows from conformance with IEEE-754, and a further hint about this behavior is given in the table in Section 17.3.

Best,

Nick Knight

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[Bernhard Schommer]

Thanks for the clarification.

Best,

-Bernhard