Public Review for RISC-V RERI non-ISA specification

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Ved Shanbhogue

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Feb 28, 2024, 9:59:23 AMFeb 28
to tech-a...@lists.riscv.org, tech-a...@lists.riscv.org
Greetings!

We are delighted to announce the commencement of the public review
period for the RISC-V RAS Error Record Register Interface (RERI)
non-ISA specification. The 30-day review period begins today, 
February 28, and concludes on March 30.

RERI augments Reliability, Availability, and Serviceability (RAS)
features in the SoC with a standard mechanism for reporting errors
by means of a memory-mapped register interface to enable error
reporting, provide the facility to log the detected errors, and
configuring means to signal the error to a RAS handler component.

The specification is available for download as a PDF here:
https://github.com/riscv-non-isa/riscv-ras-eri/releases/download/v1.0-rc2/riscv-reri.pdf

This document originates from the source available in the GitHub
repository: https://github.com/riscv-non-isa/riscv-ras-eri

To respond to the public review, please either email comments to the
public RISC-V ISA-Dev mailing list at isa...@groups.riscv.org or add
issues to the GitHub repo: https://github.com/riscv-non-isa/riscv-ras-eri/issues

Should you encounter any issues accessing the document or the GitHub
links, please do not hesitate to contact us. We are eager to provide
assistance or furnish the document in an alternative format upon request.

We value all feedback and appreciate your contribution toward refining
this specification.

Throughout the public review period, we will collect corrections,
comments, and suggestions for consideration by the Unprivileged ISA
Committee. Minor corrections and/or non-controversial changes will be
incorporated into the specification directly. Any unresolved issues or
proposed modifications will be detailed in the public review summary
report. Assuming no issues necessitate incompatible changes to the
specification under review, the SoC Infrastructure HC will propose
that the updated specifications be ratified by both the RISC-V
Technical Steering Committee and the RISC-V Board of Directors.

We extend our gratitude to all contributors for their dedicated
efforts.

Regards,
Greg Favor
Ved Shanbhogue

Ved Shanbhogue

unread,
Apr 5, 2024, 12:20:50 PMApr 5
to RISC-V ISA Dev, Ved Shanbhogue, tech-a...@lists.riscv.org
Greetings !

The review period for RISC-V RAS Error Record Register
Interface (RERI) non-ISA specification concluded on
March 27.

During the review period:
- Mark Hill suggested [1] widening the impl_id field to 32-bits.
  This suggestion was accepted [2].
- David Kruckemeyer requested clarifications and additional
   SW guidance in [3]. These clarifications and updates were
   made to the specification [4].

We extend our thanks to all who contributed valuable insights
during the review.

regards
Greg Favor
Ved Shanbhogue

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