Re: Public Review for RISC-V CBQRI and Ssqosid specifications

115 views
Skip to first unread message

Eric Shiu

unread,
Mar 5, 2024, 12:01:37 PMMar 5
to isa...@groups.riscv.org, tech-a...@lists.riscv.org, ambika.kri...@intel.com, Vedvyas Shanbhogue
Resend to include ISA-Dev group.

-Eric

On Tue, Mar 5, 2024 at 8:27 AM Eric Shiu <es...@rivosinc.com> wrote:
Greetings!

We are delighted to announce the commencement of the public review
period for the RISC-V Capacity and Bandwidth QoS Register Interface
(CBQRI) non-ISA specification and a related RISC-V QoS identifiers
(Ssqosid) fast track ISA extension. The 30-day review period begins
today, March 5, and concludes on April 4.

The CBQRI specification defines a standard register interface to
configure capacity and bandwidth allocation for workloads and the
Ssqosid specification provides a CSR for associating QoS IDs with
requests made by workloads to such controllers.

The CBQRI specification is available for download as a PDF here:
https://github.com/riscv-non-isa/riscv-cbqri/releases/download/v1.0-rc2/riscv-cbqri.pdf
This document originates from the source available in the GitHub
repository: https://github.com/riscv-non-isa/riscv-cbqri

The Ssqosid specification is available for download as a PDF here:
https://github.com/riscv/riscv-ssqosid/releases/download/v1.0-rc2/riscv-ssqosid.pdf
This document originates from the source available in the GitHub
repository: https://github.com/riscv/riscv-ssqosid

To respond to the public review, please either email comments to the
public RISC-V ISA-Dev mailing list at isa...@groups.riscv.org or add
issues to the GitHub repo:
    https://github.com/riscv-non-isa/riscv-cbqri/issues
    https://github.com/riscv/riscv-ssqosid/issues

Should you encounter any issues accessing the document or the GitHub
links, please do not hesitate to contact us. We are eager to provide
assistance or furnish the document in an alternative format upon request.

We value all feedback and appreciate your contribution toward refining
this specification.

Throughout the public review period, we will collect corrections,
comments, and suggestions for consideration by the SoC Infrastructure
HC and Privileged ISA Committee. Minor corrections and/or
non-controversial changes will be incorporated into the specification
directly. Any unresolved issues or proposed modifications will be
detailed in the public review summary report. Assuming no issues
necessitate incompatible changes to the specification under review,
the SoC Infrastructure HC and Privileged ISA Committee will propose
that the updated specifications be ratified by both the RISC-V
Technical Steering Committee and the RISC-V Board of Directors.

We extend our gratitude to all contributors for their dedicated
efforts.

Regards,
Eric Shiu
Ambika Krishnamoorthy

Eric Shiu

unread,
Apr 12, 2024, 2:15:35 PMApr 12
to RISC-V ISA Dev, Eric Shiu, ambika.kri...@intel.com, Vedvyas Shanbhogue, tech-a...@lists.riscv.org
Greetings!The review period for the RISC-V CBQRI non-ISA specification and its related
Ssqosid ISA extension concluded on April 4.
During the review period, Martin Maas provided feedback in issue #26 [1],
summarized as follows:
1. Equation 1, when rendered as a PDF, dropped an "&" symbol. This rendering
   issue has been fixed.
2. Clarification was requested on why the method to associate QoS IDs with
   devices is unspecified. The text in Section 2.1.2 was updated to clarify
   that when the system does not include an IOMMU, the method is
   implementation-specific.
3. It was suggested that considering prefetch and demand misses as additional
   address translations may be worth exploring. This enhancement should be
   considered for a future extension.
4. It was suggested that an enhancement to provide a method to snapshot multiple
   counters may be useful. This enhancement should be considered for a future
   extension.
5. Clarification was sought on the enumeration of the hierarchy of bandwidth
   controllers. It was clarified in the issue that this is being defined by a
   related ACPI extension, and the guidelines for the enumeration are included
   in Section 7.1. Additional guidelines for enumeration have been added to this
   section.
6. It was suggested that an enhancement to read an aggregation of counters
   across multiple controllers should be considered for a future extension,
   along with the freeze/snapshot extension.
7. Clarification was sought on how many RCIDs and MCIDs can be effective at the
   same time. Section 2.0 was updated to clarify that all supported RCIDs and
   MCIDs may be effective simultaneously.
8. Clarification was requested on whether bandwidth scales linearly with the
   Rbwb parameter and whether the block is specified in absolute memory
   bandwidth values. It was pointed out that the specification leaves the
   absolute bandwidth represented by a bandwidth block as unspecified. A
   clarification was included in the specification that bandwidth scales
   linearly with the number of bandwidth blocks.
The clarifications summarized above were incorporated into the specification by
PR #27 [2].
We extend our thanks to all who contributed valuable insights during the review.Regards,
Eric Shiu
Ambika Krishnamoorthy
[1] https://github.com/riscv-non-isa/riscv-cbqri/issues/26
[2] https://github.com/riscv-non-isa/riscv-cbqri/pull/27
Reply all
Reply to author
Forward
Message has been deleted
0 new messages