Writing mie.MEIE

[Vincent Lai]

In v1.9.1 privileged architecture specification, section 3.1.13 (mip and mie), it says:

"........, while mie is the corresponding XLEN-bit read/write register containing interrupt enable bits."

....

....

"There is a separate external interrupt-enable bit, named MEIE, HEIE, SEIE, and UEIE for 

M-mode, H-mode, S-mode, and U-mode external interrupts respectively."

So from these phrases, I assume that mie.MEIE (mie(11)) can be written by a CSR write instruction.

However, when I check the source code of spike, it seems that mie.MEIE cannot be written. (processor.cc, line:341, 292, 293)

Can mie.MEIE be written by a CSR write instruction? 

If the answer is NO, then how mie.MEIE is enabled/disabled for PLIC external interrupts?

Thanks!

Vincent

[Michael Clark]

mie.MEIE should be able to be written by M-mode software. M-mode should be able to set any bit in mie.

mie.SEIE should be able to be written by S-mode software (and has effect in the case that interrupts are delegated).

however mip.MEIP (the interrupt pending bit) should be set by the hardware / the PLIC.

[Michael Clark]

I should have said sie.SEIE for S-mode however sie is an alias for mie with a read/write mask allowing access to S-mode bits and below.

I would presume from the specification that the mode specific masks are somewhat like this:

/*
 * mip/mie                           33222222222211111111110000000000
 *                                   10987654321098765432109876543210
 *                                                       MHSUMHSUMHSU
 *                                                       EEEETTTTSSSS
 * Machine Read/Write Bits         M 11111111111111111111111111111111
 * Hypervisor Read/Write Bits      H 00000000000000000000011101110111
 * Supervisor Read/Write Bits      S 00000000000000000000001100110011
 * User Read/Write Bits            U 00000000000000000000000100010001
 */
const typename P::ux mi_mask       = typename P::ux(-1);
const typename P::ux hi_mask       = 0b011101110111;
const typename P::ux si_mask       = 0b001100110011;
const typename P::ux ui_mask       = 0b000100010001;

however mip.MEIP (the interrupt pending bit) should be set by the hardware / the PLIC.

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[Vincent Lai]

I have written a reset handler to write mie.MEIE in spike. And it is confirmed that spike does not allow me to write mie.MEIE.
This behavior is the same as my understanding from reading the spike source code.

This behavior is not clearly described in the spec v1.9.1. Is this a spike bug or correct behavior?

Can the spec v1.9.1 authors come out to answer my question?

If it is correct, then how mie.MEIE is enabled/disabled for PLIC external interrupts?

Thanks for the help!

Vincent