Building/installing riscv-spike simulator with vector extension

[Boul chandra Garai]

Hi, can you please help me with the pointer and procedures to follow for building/installing the riscv-spike simulator with vector extension?

[Tommy Murphy]

You shouldn't have to do anything special to build it with vector extension support. 

Spike should support vector extensions by default. 

* https://github.com/riscv-software-src/riscv-isa-sim?tab=readme-ov-file#about

> * V extension, v1.0 (requires a 64-bit host)

Are you sure that you're passing the appropriate --isa option for your needs? E.g. `--isa rv64gcv` perhaps?

* https://github.com/riscv-software-src/riscv-isa-sim/blob/2d7af2fb56937171b9794205d854a85b0dd41bb4/spike_main/spike.cc#L44

Perhaps if you clarify the nature of the problem that you're having and how you're running Spike it would help others to offer advice?

[Rishiyur Nikhil]

Does anyone know what this story is about?

The title seems absurd, so I suspect it's much ado about nothing,
but it's behind a paywall, so I'm unable to read it.

The link appeared in a recent ACM Tech News digest.

    "Scientists find security risk in RISC-V open-source chip architecture
     that China hopes can help sidestep US sanctions"

    https://www.scmp.com/news/china/science/article/3265493/scientists-find-security-risk-risc-v-open-source-chip-architecture-china-hopes-can-help-sidestep-us

Nikhil

[Boul chandra Garai]

Thank you very much for your answer. Yes, while building I have used the ../configure --prefix=$riscv --with-isa=RV64GCV.

First I build the $ git clone https://github.com/riscv/riscv-gnu-toolchain

with ../configure --prefix=$riscv --with-arch=rv64gcv --with-abi=lp64d --enable-multilib

Then I build the spike $ git clone https://github.com/riscv/riscv-isa-sim.git

with ../configure --prefix=$riscv --with-isa=RV64GCV

and then I build $ git clone https://github.com/riscv/riscv-pk

with ../configure --prefix=$riscv --host=riscv64-unknown-elf

Can you please check if all the above steps are correct even also the git link?

How to verify if the installation is supporting risc-v vector extension?

It will be really helpful if you can suggest some test code to verify the installation.

When I am giving the following command, there it is not showing the RISC-V vector extension:

$ riscv64-unknown-elf-gcc --target-help
The following options are target specific:
  -mabi=                      Specify integer and floating-point calling convention.
  -malign-data=               Use the given data alignment.
  -march=                     Generate code for given RISC-V ISA (e.g. RV64IM).  ISA strings must be lower-case.
  -mbig-endian                Assume target CPU is configured as big endian.
  -mbranch-cost=N             Set the cost of branches to roughly N instructions.
  -mcmodel=                   Specify the code model.
  -mcpu=PROCESSOR             Use architecture of and optimize the output for PROCESSOR.
  -mcsr-check                 Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA
                              is set.  The read-only CSR can not be written by the CSR instructions.
  -mdiv                       Use hardware instructions for integer division.
  -mexplicit-relocs           Use %reloc() operators, rather than assembly macros, to load addresses.
  -mfdiv                      Use hardware floating-point divide and square root instructions.
  -minline-atomics            Always inline subword atomic operations.
  -misa-spec=                 Set the version of RISC-V ISA spec.
  -mlittle-endian             Assume target CPU is configured as little endian.
  -mplt                       When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
  -mpreferred-stack-boundary= Attempt to keep stack aligned to this power of 2.
  -mrelax                     Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses.
  -mriscv-attribute           Emit RISC-V ELF attribute.
  -msave-restore              Use smaller but slower prologue and epilogue code.
  -mshorten-memrefs           Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow more memory accesses to be generated as compressed
                              instructions.  Currently targets 32-bit integer load/stores.
  -msmall-data-limit=N        Put global and static data smaller than <number> bytes into a special section (on some targets).
  -mstack-protector-guard-offset= Use the given offset for addressing the stack-protector guard.
  -mstack-protector-guard-reg= Use the given base register for addressing the stack-protector guard.
  -mstack-protector-guard=    Use given stack-protector guard.
  -mstrict-align              Do not generate unaligned memory accesses.
  -mtune=PROCESSOR            Optimize the output for PROCESSOR.

  Supported ABIs (for use with the -mabi= option):
    ilp32 ilp32d ilp32e ilp32f lp64 lp64d lp64f

  Known code models (for use with the -mcmodel= option):
    medany medlow

  Supported ISA specs (for use with the -misa-spec= option):
    2.2 20190608 20191213

  Known data alignment choices (for use with the -malign-data= option):
    natural xlen

  Valid arguments to -mstack-protector-guard=:
    global tls

  Known valid arguments for -mcpu= option:
    sifive-e20 sifive-e21 sifive-e24 sifive-e31 sifive-e34 sifive-e76 sifive-s21 sifive-s51 sifive-s54 sifive-s76 sifive-u54 sifive-u74 thead-c906

  Known valid arguments for -mtune= option:
    rocket sifive-3-series sifive-5-series sifive-7-series thead-c906 size sifive-e20 sifive-e21 sifive-e24 sifive-e31 sifive-e34 sifive-e76 sifive-s21 sifive-s51 sifive-s54 sifive-s76 sifive-u54 sifive-u74 thead-c906

Assembler options
=================

Use "-Wa,OPTION" to pass "OPTION" to the assembler.

RISC-V options:
  -fpic or -fPIC              generate position-independent code
  -fno-pic                    don't generate position-independent code (default)
  -march=ISA                  set the RISC-V architecture
  -misa-spec=ISAspec          set the RISC-V ISA spec (2.2, 20190608, 20191213)
  -mpriv-spec=PRIVspec        set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)
  -mabi=ABI                   set the RISC-V ABI
  -mrelax                     enable relax (default)
  -mno-relax                  disable relax
  -march-attr                 generate RISC-V arch attribute
  -mno-arch-attr              don't generate RISC-V arch attribute
  -mcsr-check                 enable the csr ISA and privilege spec version checks
  -mno-csr-check              disable the csr ISA and privilege spec version checks (default)
  -mbig-endian                assemble for big-endian
  -mlittle-endian             assemble for little-endian

Linker options
==============

Use "-Wl,OPTION" to pass "OPTION" to the linker.

elf64lriscv:
  --relax-gp                  Perform GP relaxation
  --no-relax-gp               Don't perform GP relaxation
  --check-uleb128             Check if SUB_ULEB128 has non-zero addend
  --no-check-uleb128          Don't check if SUB_ULEB128 has non-zero addend
elf32lriscv:
  --relax-gp                  Perform GP relaxation
  --no-relax-gp               Don't perform GP relaxation
  --check-uleb128             Check if SUB_ULEB128 has non-zero addend
  --no-check-uleb128          Don't check if SUB_ULEB128 has non-zero addend
elf64briscv:
  --relax-gp                  Perform GP relaxation
  --no-relax-gp               Don't perform GP relaxation
  --check-uleb128             Check if SUB_ULEB128 has non-zero addend
  --no-check-uleb128          Don't check if SUB_ULEB128 has non-zero addend
elf32briscv:
  --relax-gp                  Perform GP relaxation
  --no-relax-gp               Don't perform GP relaxation
  --check-uleb128             Check if SUB_ULEB128 has non-zero addend
  --no-check-uleb128          Don't check if SUB_ULEB128 has non-zero addend

--

Thanks & Regards

Mr. BOUL CHANDRA GARAI
e-mail:bga...@ursc.gov.in
Ph: 080-25082307(O)/66469103(R)

[Tommy Murphy]

These steps for building the tools should be adequate:

```

git clone https://github.com/riscv-collab/riscv-gnu-toolchain

cd riscv-gnu-toolchain

./configure --prefix=... --with-arch=rv64gcv --with-abi=lp64d --with-sim=spike

make && make build-sim

```

And then run spike with `--isa rv64gcv`.

You haven't really explained what specific problem you're having.

If you are looking for example vector code (didn't you already write some and posted in a different thread about it?!) then a quick internet search should find some.

Some of the open/closed `riscv-gnu-toolchain` issues should have some:

* https://github.com/riscv-collab/riscv-gnu-toolchain/issues?q=is%3Aissue+vector

> When I am giving the following command, there it is not showing the RISC-V vector extension:

> $ riscv64-unknown-elf-gcc --target-help

If you built the toolchain using the instructions above then the default `arch/abi` is already `rv64gcv/lp64d` so you don't need to specify this again using `-march=rv64gcv -mabi=lp64d` when compiling your code as it's already implied.

As mentioned already the Spike option for specifying the target ISA is `--isa=...`

* https://github.com/riscv-software-src/riscv-isa-sim/blob/2d7af2fb56937171b9794205d854a85b0dd41bb4/spike_main/spike.cc#L44

[Tommy Murphy]

FWIW ... https://twitter.com/chrisrohlf/status/1799846491776827642

"This story is somewhat misleading. These researchers haven’t published their findings, so we don’t know if it’s an issue in one of the RISC-V ISA specifications as it’s defined or in a specific hardware implementation of RISC-V."

[Boul chandra Garai]

This is great, thank you so much! Will try to rebuild it again afresh.

[Tommy Murphy]

I omitted `--enable-multilib` in my instructions so if you need it then add that back into the `configure` command.

However if you're only ever targeting `rv64gcv/lp64d` then you probably don't need it.

[Rishiyur Nikhil]

Ok, I have now heard directly from someone (who seems to know more
detail) that this was a specific side-channel vulnerability in a
particular implementation.  No surprise.

Which seems to confirm: this is much ado about nothing.

It seems that either the researchers, or their press channels,
continue to confuse and mislead between "ISA" and "implementation"
and, without cause, bring in irrelevant but hot-topic phrases like
"sidestep US sanctions".

I wish ACM Tech News would not participate in circulating these kinds
of stories, without vetting.

Nikhil

[Tommy Murphy]

> It seems that either the researchers, or their press channels, continue to confuse and mislead between "ISA" and "implementation"

Maybe not really that surprising when so many, including some who really should know better, mistakenly refer to RISC-V as "open-source" even after many clarifications on the issue, e.g.:

https://riscv.org/blog/2020/02/risc-v-is-not-an-open-source-processor-krste-asanovic-chairman-of-the-board-risc-v/ 

[Philipp Tomsich]

This paper described a potential timing side-channel on SonicBOOM
based on register write-port contention and the arbitration scheme
between divide-results and other ALU-results.
The exploitation is described only theoretically and none of us has
seen a PoC exploit so far.

--Philipp.

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[Tommy Murphy]

Thanks, Philipp. So, this? 

* https://github.com/riscv-boom/riscv-boom

Are there any silicon (ASIC, not FPGA) implementations of/based on this in the wild that are not, say, just academic/research implementations?

[Tommy Murphy]

Sorry, I should've checked first. ChatGPT gave me this:

"Yes, there are commercial implementations of RISC-V processors based on the Sonic BOOM (Berkeley Out-of-Order Machine) core. One prominent example is the "U740" processor from SiFive, which is part of their high-performance portfolio. The U740 integrates Sonic BOOM cores to deliver high processing power suitable for advanced computing tasks."

[Bruce Hoult]

I'm not sure what the "U740" is, but the U74 core, U74-MC core complex
(licenced by e.g. StarFive for their JH7110 SoC), and SiFive's own
FU-740 SoC in their HiFive Unmatched all are (or use) the U74 core
which is an in-order dual-issue core, not OoO, and thus certainly not
based on Sonic BOOM. The core was also announced a couple of years
before Sonic BOOM.

Oh ... apparently the FU-740 is sometimes known as U740.

On Mon, Jun 17, 2024 at 8:26 PM Tommy Murphy <tommy_...@hotmail.com> wrote:
>
> Sorry, I should've checked first. ChatGPT gave me this:
>
> "Yes, there are commercial implementations of RISC-V processors based on the Sonic BOOM (Berkeley Out-of-Order Machine) core. One prominent example is the "U740" processor from SiFive, which is part of their high-performance portfolio. The U740 integrates Sonic BOOM cores to deliver high processing power suitable for advanced computing tasks."
>

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[Krste Asanovic]

Bruce is correct, ChatGPT is wrong.
The SiFive U74 core is not based on SonicBoom.
SiFive does not have a product named U740.
Krste

> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAMU%2BEkwxwrDghnBBf%3DxsX4T7CUgz2jwpRQoHQMuogwJRs5oKTQ%40mail.gmail.com.

[Tommy Murphy]

> SiFive does not have a product named U740.

What about this?

* https://www.sifive.com/boards/hifive-unmatched

"The development board is powered by the SiFive Freedom U740 (FU740), an SoC that includes a high-performance multi-core, 64-bit dual-issue, superscalar RISC-V processor (SiFive Essential™ U74-MC) with 16GB of DDR4, Gigabit Ethernet, PCIe expansion, USB 3, and M.2 sockets for Wi-Fi, Bluetooth and NVMe storage."

Is the [F]U740 based on SonicBOOM?

[Krste Asanovic]

Oops - I was wrong - product marketing changed the name.

Krste

[Boul chandra Garai]

Thank you very much for the tip!  I was able to build the riscv-gnu toolchain after following your instructions. Could you guide me for the riscv-llvm building, what configuration should I use?

Right now I have used the configuration as follows:

./configure --prefix=$RISCV --with-arch=rv64gcv --with-abi=lp64d --with-sim=spike --enable-multilib

On Sun, Jun 16, 2024 at 10:47 PM Tommy Murphy <tommy_...@hotmail.com> wrote:

I omitted `--enable-multilib` in my instructions so if you need it then add that back into the `configure` command.

However if you're only ever targeting `rv64gcv/lp64d` then you probably don't need it.

[Tommy Murphy]

> Could you guide me for the riscv-llvm building

See here: 

* https://github.com/riscv-collab/riscv-gnu-toolchain?tab=readme-ov-file#llvm--clang

> what configuration should I use?

If you're targeting rv64gcv/lp64d then presumably this is appropriate?

> Right now I have used the configuration as follows:

./configure --prefix=$RISCV --with-arch=rv64gcv --with-abi=lp64d --with-sim=spike --enable-multilib

If you're *only* targeting rv64gcv/lp64d then you don't really need --enable-multilib.