Fast Interrupts Task Group

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Krste Asanovic

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Mar 26, 2018, 5:59:28 AM3/26/18
to isa...@groups.riscv.org

We have now created a Fast Interrupts Task Group with the following
charter:

Fast Interrupts Task Group Charter
Chair: Krste Asanovic, UCB, Co-Chair: Kevin Chen, Andes

Develop a low-latency, vectored, priority-based, preemptive interrupt scheme
for interrupts directed to a single hart, compatible with the existing RISC-V
standards and extensible to multi-core. Provide both hardware specifications
and software ABIs/APIs. Standardize compiler conventions for annotating
interrupt handler functions.


Foundation members please join using the Kavi workspace, and we'll
schedule and start meetings shortly.

Krste

Xiang Xiao

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Nov 7, 2018, 10:20:29 PM11/7/18
to RISC-V ISA Dev
Hi Krste,
What the current state for Fast Interrupt? When the spec(or draft) will release to public?

Thanks
Xiang

Jim Wilson

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Nov 7, 2018, 11:38:28 PM11/7/18
to xiaoxia...@gmail.com, isa...@groups.riscv.org
On Wed, Nov 7, 2018 at 7:20 PM Xiang Xiao <xiaoxia...@gmail.com> wrote:
> What the current state for Fast Interrupt? When the spec(or draft) will release to public?

https://github.com/sifive/clic-spec

I think the hope is that we can finish it soon.

Jim

Xiang Xiao

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Nov 8, 2018, 1:21:00 AM11/8/18
to Jim Wilson, isa...@groups.riscv.org
Thanks, Jim. I am reading this spec now.

-----邮件原件-----
发件人: Jim Wilson [mailto:ji...@sifive.com]
发送时间: 2018年11月8日 12:38
收件人: xiaoxia...@gmail.com
抄送: isa...@groups.riscv.org
主题: Re: [isa-dev] Re: Fast Interrupts Task Group
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