SPEC2017 dynamic instruction count vs ARMv8

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Mehul Shah

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Apr 12, 2021, 2:35:31 PM4/12/21

to RISC-V ISA Dev

Hi,

I'm curious if there is a more recent version of the July 2016 paper "Renewed case for RISC : Avoiding ISA bloat ..." showing a comparison between RISCV and ARMv8 of dynamic instruction counts for SPEC2017 workloads (Table II in that paper) with latest ISA extensions.

Can someone share a recipe for SPEC2017 with GCC version, ISA extensions, etc. ? I see significant bloat on x264 in particular, which I am unable to explain.

thanks,

/mehul

Mehul Shah

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Apr 12, 2021, 2:36:38 PM4/12/21

to RISC-V ISA Dev, Mehul Shah

https://arxiv.org/abs/1607.02318

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