Vector Segment Load/Store Encoding

[Tor Jeremiassen]

Reading through the RiscV "V" Vector Extensions 1.0, I cannot find the encodings for the vector load/store segment instructions (unit stride, strided, indexed). All the other load instructions seem to be well described. Does anyone have any pointers?

[Nick Knight]

Hi Tor,

Are you looking at Section 7.1 (p.29) of the ratified spec: https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf ?

A key detail is that "nf[2:0]" indicates the segment size.

Best,

Nick Knight

On Thu, Jun 2, 2022 at 4:49 PM 'Tor Jeremiassen' via RISC-V ISA Dev <isa...@groups.riscv.org> wrote:

Reading through the RiscV "V" Vector Extensions 1.0, I cannot find the encodings for the vector load/store segment instructions (unit stride, strided, indexed). All the other load instructions seem to be well described. Does anyone have any pointers?

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[Tor Jeremiassen]

So the segmented load/stores differ from the other loads/stores only in nf[2:0] != 0? I.e., a segment load/store with segment size 1, is really just a regular load/store.

[Nick Knight]

Yes, this is clarified in the last two paragraphs of Section 7.2:

The nf[2:0] field encodes the number of fields in each segment. For regular vector loads and stores, nf=0, indicating that a single value is moved between a vector register group and memory at each element position. Larger values in the nf field are used to access multiple contiguous fields within a segment as described below in Section Vector Load/Store Segment Instructions.

The nf[2:0] field also encodes the number of whole vector registers to transfer for the whole vector register load/store instructions.

Best,

Nick Knight