Public review for standard extension Sstc

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Stephano Cetola

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Sep 16, 2021, 8:11:44 PM9/16/21
to isa...@groups.riscv.org, Greg Favor, Andrew Waterman
We are delighted to announce the start of the public review period for
the following proposed standard extension to the RISC-V ISA:
Sstc - S and VS level Time Compare

The review period begins today, Thursday Sept 16, and ends on Sunday
Oct 31 (inclusive).

This extension is part of the Privileged Specification.

This extension is described in the PDF spec available at:
https://drive.google.com/file/d/1f4DyxZMzl3yH7KGKXJFZ_iUY_AU9az_K/view?usp=sharing

To respond to the public review, please email comments to the public
isa-dev mailing list. We welcome all input and appreciate your time
and effort in helping us by reviewing the specification.

During the public review period, corrections, comments, and
suggestions, will be gathered for review by the Privileged ISA
Committee. Any minor corrections and/or uncontroversial changes will
be incorporated into the specification. Any remaining issues or
proposed changes will be addressed in the public review summary
report. If there are no issues that require incompatible changes to
the public review specification, the Privileged ISA Committee will
recommend the updated specifications be approved and ratified by the
RISC-V Technical Steering Committee and the RISC-V Board of Directors.

Thanks to all the contributors for all their hard work.

Kind Regards,
Stephano
--
Stephano Cetola
Director of Technical Programs
RISC-V International

Stephano Cetola

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Sep 17, 2021, 7:48:00 PM9/17/21
to RISC-V ISA Dev, Greg Favor, andrew
Apologies on the mixup, the latest version of the spec is here:

Paul Donahue

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Oct 5, 2021, 5:02:28 PM10/5/21
to RISC-V ISA Dev, step...@riscv.org, Greg Favor, andrew
Sstc says that mcounteren.TM controls S-mode access to stimecmp and that hcounteren.TM controls VS-mode access to vstimecmp.  Should mcounteren.TM also control HS/VS access to vstimecmp?  If mcounteren.TM=0 then the value of time should presumably be hidden from both direct and indirect access by HS-mode.  However, if mcounteren.TM does not affect vstimecmp then HS-mode could discover the value of time by repeatedly writing vstimecmp and observing the effect on hip.VSTIP.

Also, VS-mode accesses to vstimecmp (via stimecmp) will raise a virtual instruction exception if hcounteren.TM=0 and mcounteren.TM=1 but there is no VS-mode exception specified if mcounteren.TM=0.  This leads to a similar problem where VS-mode can indirectly discover the value of time+htimedelta.


Thanks,

-Paul

John Hauser

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Oct 22, 2021, 1:41:23 AM10/22/21
to RISC-V ISA Dev
Paul Donahue wrote:
> Sstc says that mcounteren.TM controls S-mode access to stimecmp
> and that hcounteren.TM controls VS-mode access to vstimecmp.
> Should mcounteren.TM also control HS/VS access to vstimecmp?  If
> mcounteren.TM=0 then the value of time should presumably be hidden from
> both direct and indirect access by HS-mode.  However, if mcounteren.TM
> does not affect vstimecmp then HS-mode could discover the value of time
> by repeatedly writing vstimecmp and observing the effect on hip.VSTIP.
>
> Also, VS-mode accesses to vstimecmp (via stimecmp) will raise a virtual
> instruction exception if hcounteren.TM=0 and mcounteren.TM=1 but there
> is no VS-mode exception specified if mcounteren.TM=0.  This leads to
> a similar problem where VS-mode can indirectly discover the value of
> time+htimedelta.

I agree.  When mcounteren.TM = 0, an attempt to access stimecmp or
vstimecmp from a privilege mode other than M should raise an illegal
instruction exception.  The Sstc document currently doesn't say that.

    - John Hauser

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