Public review for standard extensions Zwrs

[Ved Shanbhogue]

We are delighted to announce the start of the public review period for the Zwrs proposed standard extensions to the RISC-V ISA.

The review period begins today, 7/7/2022, and ends on 8/29/2022 (inclusive).

This extension is part of the Unprivileged Specification.

This extension is described in the PDF spec available at:

https://github.com/riscv/riscv-zawrs/releases/tag/V1.0-rc3

To respond to the public review, please either email comments to the public isa-dev mailing list. We welcome all input and appreciate your time and effort in helping us by reviewing the specification.

During the public review period, corrections, comments, and suggestions, will be gathered for review. Any minor corrections and/or uncontroversial changes will be incorporated into the specification. Any remaining issues or proposed changes will be addressed in the public review summary report. If there are no issues that require incompatible changes to the public review specification, the Unprivileged ISA Committee will recommend the updated specifications be approved and ratified by the RISC-V Technical Steering Committee and the RISC-V Board of Directors.

Thanks to all the contributors for all their hard work.

Ved Shanbhogue

Chair, WRS Task Group

[Tommy Murphy]

> To respond to the public review, please either email comments to the public isa-dev mailing list. 

Hi Ved

Is there a second option missing here or is there just the one way to provide feedback? 

Regards

Tommy

[Ved Shanbhogue]

On Thu, Jul 07, 2022 at 12:48:13PM +0000, Tommy Murphy wrote:
>Is there a second option missing here or is there just the one way to provide feedback?

My bad. You may also create an issue in the github.

regards
ved

[Aaron Durbin]

For the lazy :)

https://github.com/riscv/riscv-zawrs/issues

Repo in general: https://github.com/riscv/riscv-zawrs/

 

regards
ved

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[Simon Jackson]

It could work for a lot of things when low power is required. For more general poling a cache-flush-read (cache-coherent read where write order from multicores are not even necessary) is sufficient for all multitasking sync at low to medium loads. At high loads there are bottleneck considerations, but better than a full fence instruction completion.

Strangely the pattern of action sync to a memory address is useful in more than one ISA context such as the cache flush mentioned above only needing to be done on the to-be-read address. It's a good start but I suppose what I'm trying to say is split the opcode space into power/speed/efficiency parts so that the opcode space for design goals is lesser, and just a compiler flag hopefully.

Cheers

Simon