Question on constrained LR/SC loop properties

[Anirudh Kaushik]

Hello,
I would like some clarification on one of the properties listed for constrained LR/SC. Specifically, the second point of the specification mentions

An LR/SC sequence begins with an LR instruction and ends with an SC instruction. The dynamic code executed between the LR and SC instructions can only contain instructions from the base ''I'' instruction set, excluding loads, stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM instructions. Compressed forms of the aforementioned ''I'' instructions in the Zca and Zcb extensions are also permitted.

What does dynamic code executed mean here? Is this referring to code executed between an LR and paired SC by the underlying core (in-order, out-of-order)?

For example, I have the following CFG from a function in the libc library and I am reasoning about whether this is a constrained or unconstrained LR/SC loop? An out-of-order core execution could execute the lr in bb.19 followed by instructions in bb.21, bb.22 and bb.23 (due to out-of-order execution, branch speculation) and then the sc in bb.20. Since bb.23 has a lbu and this violates the above condition, is this an unconstrained LR/SC instruction sequence?

Looking forward to your response.

[Greg Favor]

It is referring to the actual instruction sequence that is executed between an LR and paired SC.  This is independent of the hart implementation, e.g. whether it is an in-order or o-o-o design.  (In other words, speculative execution by a design is not relevant; it is the committed instruction execution stream that matters.)

Greg

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