Public review for standard extensions Zfh, Zfhmin

[Stephano Cetola]

We are delighted to announce the start of the public review period for
the following proposed standard extensions to the RISC-V ISA:

Zfh - Half width floating point
Zfhmin - Subset of half width floating point

These extensions are part of the Unprivileged Specification.

The review period begins today, Thursday Sept 16, and ends on Sunday
Oct 31 (inclusive).

These extensions are described in the PDF spec available at:
https://drive.google.com/file/d/1GJb230aA2HKkRJ2jqw5bRL0q3FOPQMrN/view?usp=sharing

To respond to the public review, please email comments to the public
isa-dev mailing list. We welcome all input and appreciate your time
and effort in helping us by reviewing the specification.

During the public review period, corrections, comments, and
suggestions, will be gathered for review by the Unprivileged ISA
Committee. Any minor corrections and/or uncontroversial changes will
be incorporated into the specification. Any remaining issues or
proposed changes will be addressed in the public review summary
report. If there are no issues that require incompatible changes to
the public review specification, the Unprivileged ISA committee will
recommend the updated specifications be approved and ratified by the
RISC-V Technical Steering Committee and the RISC-V Board of Directors.

Thanks to all the contributors for all their hard work.

Kind Regards,
Stephano
--
Stephano Cetola
Director of Technical Programs
RISC-V International

[Torbjørn Viem Ness]

Hi Stephano, and thanks to all contributors to this extension - it looks solid!

I just wonder about one thing in a footnote:

"Although this extension provides explicit conversion instructions that suffice to implement that pattern, future extensions might further accelerate such computation with additional instructions that implicitly widen their operands—e.g., half⇥half+single!single—or implicitly narrow their results—e.g., half+single!half."

Have there been any thoughts on how to encode the formats of operands and results in such instructions? I guess it would make sense to use the fmt field to denote the resulting format, but how would the rest be encoded - just variations in the funct5 field (if they're not all taken) or a new opcode? In the case of FMA instructions the encoding space is all filled, unless one of the reserved rounding modes are to be used.

[Andrew Waterman]

On Fri, Sep 17, 2021 at 5:01 AM Torbjørn Viem Ness <tbn...@gmail.com> wrote:

Hi Stephano, and thanks to all contributors to this extension - it looks solid!

I just wonder about one thing in a footnote:

"Although this extension provides explicit conversion instructions that suffice to implement that pattern, future extensions might further accelerate such computation with additional instructions that implicitly widen their operands—e.g., half⇥half+single!single—or implicitly narrow their results—e.g., half+single!half."

Have there been any thoughts on how to encode the formats of operands and results in such instructions? I guess it would make sense to use the fmt field to denote the resulting format, but how would the rest be encoded - just variations in the funct5 field (if they're not all taken) or a new opcode? In the case of FMA instructions the encoding space is all filled, unless one of the reserved rounding modes are to be used.

A subset of the architecture-review committee did discuss this topic, and our immediate reaction was the same as yours: repurpose the rounding-mode field and restrict those operations to dynamic rounding only.  But, of course, it was an informal discussion, and no decision is likely to be made any time soon, since there has been little demand for that hypothetical extension.

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