Processors that implement Svpbmt

Michael Zoran

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Jan 22, 2023, 1:43:32 AM1/22/23

to RISC-V ISA Dev

Anybody know of any processor implementations that support Svpbmt? Possibly anything from SiFive?

Tommy Murphy

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Jan 22, 2023, 9:00:52 AM1/22/23

to Michael Zoran, RISC-V ISA Dev

I presume that you mean ASIC or FPGA RISC-V implementations rather than simulator implementations such as QEMU, Spike etc.?

Michael Zoran

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Jan 22, 2023, 4:24:54 PM1/22/23

to RISC-V ISA Dev, Tommy Murphy, Michael Zoran

Yes, I'm only interested in ASIC. Not FPGA implementations.

Michael Zoran

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Jan 22, 2023, 4:25:45 PM1/22/23

to RISC-V ISA Dev, Michael Zoran, Tommy Murphy

A simulator implementation isn't what I'm looking for at this point either.

Tommy Murphy

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Jan 23, 2023, 6:08:51 AM1/23/23

to Michael Zoran, RISC-V ISA Dev, Michael Zoran

Any use?

https://www.sifive.com/press/sifives-new-high-performance-processors-offer-a-significant

"Full RISC-V RVA22 profile compliance"

Svpbmt is a mandatory extension in RVA22S64:

https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#622-rva22s64-mandatory-extensions

Bruce Hoult

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Jan 28, 2023, 4:38:39 AM1/28/23

to Tommy Murphy, Michael Zoran, RISC-V ISA Dev

Which raises the question of whether the OP wants RTL or an off the shelf chip :-)

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Michael Zoran

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Jan 28, 2023, 10:01:49 AM1/28/23

to RISC-V ISA Dev, Bruce Hoult, Michael Zoran, RISC-V ISA Dev, Tommy Murphy

I'm looking for a dev board.

I ordered one from starfive and I'm trying to get a hold of the new one from sifive.

Tommy Murphy

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Jan 28, 2023, 10:32:34 AM1/28/23

to Michael Zoran, RISC-V ISA Dev, Bruce Hoult, Michael Zoran, RISC-V ISA Dev

What StarFive CPU implements Svpbmt?

Michael Zoran

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Jan 28, 2023, 10:42:41 AM1/28/23

to RISC-V ISA Dev, Tommy Murphy, Bruce Hoult, Michael Zoran, RISC-V ISA Dev

As far as I know, it doesn't.

The in development Hifive Pro from sifive apparently does.

On Saturday, January 28, 2023 at 9:32:34 AM UTC-6 Tommy Murphy wrote:

What StarFive CPU implements Svpbmt?

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