Cache control from VM page tables

[mzoran]

I was wondering if anybody has considered adding data cache control to VM page tables for RISC-V like many other architectures seem to have?  I noticed that the page table format for both 32bit and 64bit have a few extra bits which are not currently used.

The application I'm thinking about is something like PCIe.  The peripherals don't have a static physical address and may possibly be expanded later so the traditional RISCV approach of marking the addresses in the PMP may not work well.

One example is a physical M2 slot device that contains some amount of RAM(which may be marked as cachable) plus some control registers which would not be marked as cachable.

[Kelvin Goveas]

Hi,

I am not sure exactly what you mean by "data cache control" but the svpbmt extension uses bits 62:61 of the leaf PTE to specify a 2-bit memory type, which based on the value, can override the memory type specified in the platform specific PMA registers. This extension has been ratified and is described in chapter 6 of the RV privileged spec.

Kelvin