Why SPIE must set to 1 when execute SRET?

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DuongComputing

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Jun 27, 2020, 6:51:38 AM6/27/20
to RISC-V ISA Dev
Dear all,

I have a concern about interrupt as below:

"The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1"

Why SPIE must set to 1 when execute SRET?

Best regards,
Duong Tran

Allen Baum

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Jun 29, 2020, 3:48:19 AM6/29/20
to DuongComputing, RISC-V ISA Dev
This is a good question. 
It is not obvious why that is "the" right answer, or whether there is a "right" answer, but it has to be set to something.

I think this only matters after returning a nested trap,  e.g.  a first trap into S-mode there was something that caused entry to Smode, and then a second horizontal Smode->Smode trap. That second entry will effectively overwrite the value of SPIE.
When the second trap occurs,  the original SPIE is overwritten, and either it's a fatal bug (because you've lost the earlier value of SPIE), or the S-mode code anticipated the possibility and saved SPIE, so will restore the value before returning This overwrites the "1" that was filled in by the return from the second (nested) trap. So, if this analysis is correct, I'm not sure when it would make a difference what value is set in this case, but it is deterministic.

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kr...@berkeley.edu

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Jun 30, 2020, 12:18:25 PM6/30/20
to Allen Baum, DuongComputing, RISC-V ISA Dev

It should not be used in practice, but we wanted the value to be
deterministic.

The rationale for the actual value is that accidental stack underflow
leaves interrupts on, which has marginally greater probability of
making error "noticeable".

Krste
| https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAF4tt%3DBG8P7bOxNWc%3DY%2B1c9fwdw56EuS_-SyS%2BvLE-5MyhftLA%40mail.gmail.com.

Đại Dương Trần

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Jul 3, 2020, 5:04:42 AM7/3/20
to kr...@berkeley.edu, Allen Baum, RISC-V ISA Dev
Dear  Mr. Krste and Mr. Allen Baum,

Thank you for explaining the meaning of setting the SPIE bit.

Best regards,
Duong Tran.

Vào Th 3, 30 thg 6, 2020 vào lúc 23:18 <kr...@berkeley.edu> đã viết:
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