RISC-V ISA Dev

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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.

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Hemanth Satyanarayana, Allen Baum4

Dec 7

RVA22 compliance

Thanks, I guess we have to do with what's available and make our own arrangments. On Thursday,

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RVA22 compliance

Thanks, I guess we have to do with what's available and make our own arrangments. On Thursday,

Dec 7

Javed Osmany, … Ved Shanbhogue4

Nov 20

Smmtt specification, PDF document

If the release is older than the last commit then a PDF can also be found in the build artefacts of

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Smmtt specification, PDF document

If the release is older than the last commit then a PDF can also be found in the build artefacts of

Nov 20

Angelo Bulfone, … Bruce Hoult4

Nov 15

Division rounding extensions?

I believe the following is a valid implementation of floor division? foorDiv: srli a5,a1,63 sub a0,a0

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Division rounding extensions?

I believe the following is a valid implementation of floor division? foorDiv: srli a5,a1,63 sub a0,a0

Nov 15

Nov 15

Public review for BFloat16 (BF16) Vector and Scalar ISA extensions

We are beyond thrilled to announce the start of the public review period for the following proposed

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Public review for BFloat16 (BF16) Vector and Scalar ISA extensions

We are beyond thrilled to announce the start of the public review period for the following proposed

Nov 15

Beeman Strong, Heinrich Schuchardt3

Nov 15

Public review for ISA extension Smcsrind/Sscsrind

Hi Heinrich, Version 1.13 of the privilege spec will no longer require illegal instruction exceptions

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Public review for ISA extension Smcsrind/Sscsrind

Hi Heinrich, Version 1.13 of the privilege spec will no longer require illegal instruction exceptions

Nov 15

Mahendra Gowda, Rishiyur Nikhil3

Nov 3

Need RISC-V Assembly code

Thank you. On Thu, Nov 2, 2023 at 6:19 PM Rishiyur Nikhil <nik...@bluespec.com> wrote: Take a

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Need RISC-V Assembly code

Thank you. On Thu, Nov 2, 2023 at 6:19 PM Rishiyur Nikhil <nik...@bluespec.com> wrote: Take a

Nov 3

Teng Wu, Bruce Hoult2

Nov 1

How to test how does a RISC-V implementation process misaligned data access?

You are running in Linux or similar. Unaligned access is required to work transparently, but on many

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How to test how does a RISC-V implementation process misaligned data access?

You are running in Linux or similar. Unaligned access is required to work transparently, but on many

Nov 1

Victor Toon De Araujo, … Bruce Hoult15

Nov 1

Building RISCV-GNU-Toolchain

Building in a fresh environment in docker or some VM can be helpful if something in your long used

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Building RISCV-GNU-Toolchain

Building in a fresh environment in docker or some VM can be helpful if something in your long used

Nov 1

Eric Lorimer, … K. York12

Oct 14

Floating point atomic memory operations

If you're making a SIMT core, you're acting like a GPU and including some custom instructions

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Floating point atomic memory operations

If you're making a SIMT core, you're acting like a GPU and including some custom instructions

Oct 14

Oct 9

Re: [RISC-V tech-announce] Public review for standard extension Zacas

>We are delighted to announce the start of the public review period for >the following proposed

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Re: [RISC-V tech-announce] Public review for standard extension Zacas

>We are delighted to announce the start of the public review period for >the following proposed

Oct 9

Oct 6

Public Review: Advanced Configuration and Power Interface - Functional Fixed Hardware

We're excited to kick off the public review for ACPI FFH v1.0.0. Review Dates: 10/06/2023 to 11/

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Public Review: Advanced Configuration and Power Interface - Functional Fixed Hardware

We're excited to kick off the public review for ACPI FFH v1.0.0. Review Dates: 10/06/2023 to 11/

Oct 6

Oct 6

Public Review: Supervisor Binary Interface(SBI) v2.0

We're excited to kick off the public review for SBI v2.0. Review Dates: 10/06/2023 to 11/06/2023

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Public Review: Supervisor Binary Interface(SBI) v2.0

We're excited to kick off the public review for SBI v2.0. Review Dates: 10/06/2023 to 11/06/2023

Oct 6

Javed Osmany, … MitchAlsup13

Oct 6

Checking PMP settings synchronously

On Wednesday, October 4, 2023 at 5:16:03 AM UTC-5 Tariq Kurd wrote: This one is a thorny problem, and

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Checking PMP settings synchronously

On Wednesday, October 4, 2023 at 5:16:03 AM UTC-5 Tariq Kurd wrote: This one is a thorny problem, and

Oct 6

Sep 29

Re: [RISC-V tech-announce] Public review of Svadu Standard Extension

>The 30-day review period begins today, August 29, and ends officially >on September 27 (

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Re: [RISC-V tech-announce] Public review of Svadu Standard Extension

>The 30-day review period begins today, August 29, and ends officially >on September 27 (

Sep 29

L Peter Deutsch, … Al Martin3

Sep 18

Floating point register references in riscv-opcodes-master

In my opinion, assembly code should use fs*, but accept rs*. FP code should work whether for F (with

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Floating point register references in riscv-opcodes-master

In my opinion, assembly code should use fs*, but accept rs*. FP code should work whether for F (with

Sep 18

L Peter Deutsch, … Allen Baum13

Sep 13

Zacas specification: AMOCAS.D

Would there be an actual advantage sto allowing that? I think "interesting possibilities"

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Zacas specification: AMOCAS.D

Would there be an actual advantage sto allowing that? I think "interesting possibilities"

Sep 13

Javed Osmany, … Allen Baum6

Sep 12

Privileged Spec and number of PMP registers

Rsending so everyone can understand the reason: The issue is that while we test whether PMPs work for

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Privileged Spec and number of PMP registers

Rsending so everyone can understand the reason: The issue is that while we test whether PMPs work for

Sep 12

Joël Porquet-Lupine, … Jeff Scott4

Sep 12

rvcodec.js: a RISC-V instruction encoder/decoder

Hi all, Thanks for the feedback! I've created two tickets based on your suggestions: - Better

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rvcodec.js: a RISC-V instruction encoder/decoder

Hi all, Thanks for the feedback! I've created two tickets based on your suggestions: - Better

Sep 12

Sep 8

Public review for standard extension Zacas

Greetings! We are delighted to announce the start of the public review period for the following

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Public review for standard extension Zacas

Greetings! We are delighted to announce the start of the public review period for the following

Sep 8

Javed Osmany, … Jeff Scheel15

Sep 7

Hypervisor support with no Page Tables

Thanks Jeff for the pointer. Best regards JO On Thursday, September 7, 2023 at 12:44:29 PM UTC+1 Jeff

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Hypervisor support with no Page Tables

Thanks Jeff for the pointer. Best regards JO On Thursday, September 7, 2023 at 12:44:29 PM UTC+1 Jeff

Sep 7

Aug 29

Public review of Svadu Standard Extension

Greetings! We are delighted to announce the start of the public review period for the following

unread,

Public review of Svadu Standard Extension

Greetings! We are delighted to announce the start of the public review period for the following

Aug 29

Aug 5

RISC V Architecture for Machine learning and Deep learning

Hi, Since ML and DL speak the language of matrices more specifically Tensors, I would like to ask the

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RISC V Architecture for Machine learning and Deep learning

Hi, Since ML and DL speak the language of matrices more specifically Tensors, I would like to ask the

Aug 5

Aug 2

Public review for standard extension Smcntrpmf

We are delighted to announce the start of the public review period for the following proposed

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Public review for standard extension Smcntrpmf

We are delighted to announce the start of the public review period for the following proposed

Aug 2

Abhav S Velidi, … Bruce Hoult8

Jul 13

Few Queries on Privilege modes RISCV

Well, let's say the C extension allows 2 byte opcodes to be used for full-register loads and

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Few Queries on Privilege modes RISCV

Well, let's say the C extension allows 2 byte opcodes to be used for full-register loads and

Jul 13

Jim Kenua, … Greg Favor8

Jul 10

RISC-V privileged level walk

On Mon, Jul 10, 2023 at 3:50 PM ALin Parcalab <alinpa...@gmail.com> wrote: Good question, I

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RISC-V privileged level walk

On Mon, Jul 10, 2023 at 3:50 PM ALin Parcalab <alinpa...@gmail.com> wrote: Good question, I

Jul 10

Krste Asanovic, … Jeff Scheel11

Jun 26

Public review of Zfa Standard Extension for Additional Floating-Point Instructions

This email is being sent of behalf of Krste Asanović, Earl Killian, and Andrew Waterman. ******

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Public review of Zfa Standard Extension for Additional Floating-Point Instructions

This email is being sent of behalf of Krste Asanović, Earl Killian, and Andrew Waterman. ******

Jun 26

Robert Lipe, … L Peter Deutsch5

Jun 24

Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 3 updates in 1 topic

I too have been concerned about the proliferation of optional extensions. I know this is a recognized

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Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 3 updates in 1 topic

I too have been concerned about the proliferation of optional extensions. I know this is a recognized

Jun 24

Krste Asanovic, … Markku-Juhani O. Saarinen3

Jun 24

Public review for RISC-V Vector Cryptography Extensions

On Sat, Jun 24, 2023 at 10:56 AM James Cloos <cl...@jhcloos.com> wrote: quick q: i recently

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Public review for RISC-V Vector Cryptography Extensions

On Sat, Jun 24, 2023 at 10:56 AM James Cloos <cl...@jhcloos.com> wrote: quick q: i recently

Jun 24

Teng Wu, Bruce Hoult2

Jun 21

Are pages with U=1 executable in S-mode?

S-mode instruction fetches from pages that are accessible by U-mode will always fault. On Wed, Jun 21

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Are pages with U=1 executable in S-mode?

S-mode instruction fetches from pages that are accessible by U-mode will always fault. On Wed, Jun 21

Jun 21

thimaya panda, … Allen Baum4

Jun 19

Trap with point of no return

I'd totally forgotten about that - oops. Thanks for correcting me. On Mon, Jun 19, 2023 at 11:12

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Trap with point of no return

I'd totally forgotten about that - oops. Thanks for correcting me. On Mon, Jun 19, 2023 at 11:12

Jun 19

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