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RISC-V ISA Dev

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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.

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Jerry Ho, … Jeff Scott22

10/28/21

question on NMI

Thanks Tommy! That was very helpful and is along the same lines I would take if doing this as a

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question on NMI

Thanks Tommy! That was very helpful and is along the same lines I would take if doing this as a

10/28/21

7/6/20

Understand the custom instruction

Hi experties ..! I am trying to understand custom instruction added using a python script for orca(

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Understand the custom instruction

Hi experties ..! I am trying to understand custom instruction added using a python script for orca(

7/6/20

Sourav Roy, … Jeff Scott12

6/25/20

Delegation of machine mode interrupts

Thanks, this is clear. Jeff From: Andrew Waterman <wate...@eecs.berkeley.edu> Sent: Wednesday,

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Delegation of machine mode interrupts

Thanks, this is clear. Jeff From: Andrew Waterman <wate...@eecs.berkeley.edu> Sent: Wednesday,

6/25/20

View more pinned conversations

Shreyas Talwekar

Jul 7

RISC-V vs C Code Comparison for Simple Multiply and Accumulate (MAC) Operation

Hi, We tried profiling a simple MAC operation using both RISC-V Vector (RVV) intrinsics and plain C

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RISC-V vs C Code Comparison for Simple Multiply and Accumulate (MAC) Operation

Hi, We tried profiling a simple MAC operation using both RISC-V Vector (RVV) intrinsics and plain C

Jul 7

Paris Oplopoios

Jul 3

Extension for overflow calculation?

Hello, Emulating x86 or AArch64 on RISC-V requires emulating the flags using multiple instructions.

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Extension for overflow calculation?

Hello, Emulating x86 or AArch64 on RISC-V requires emulating the flags using multiple instructions.

Jul 3

Oleksii Kurochko

Jun 25

Call of hfence_gvma_all after update of CSR_HGATP

Hello Community, I decided to check how KVM determines a length of VMIDLEN and found the following:

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Call of hfence_gvma_all after update of CSR_HGATP

Hello Community, I decided to check how KVM determines a length of VMIDLEN and found the following:

Jun 25

Leyfoon Tan, … Allen Baum6

Jun 20

RE: Public Review for RPMI Specification

Hi all, We're pleased to announce that the latest version of the RPMI specification (v0.99) is

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RE: Public Review for RPMI Specification

Hi all, We're pleased to announce that the latest version of the RPMI specification (v0.99) is

Jun 20

Jun 20

Re: [RISC-V tech-announce] Public Review of the RISC-V Boot and Runtime Services (BRS) spec v1.0

Hi All, Re-sending public review email of RISC-V Boot and Runtime Services Specification. Please see

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Re: [RISC-V tech-announce] Public Review of the RISC-V Boot and Runtime Services (BRS) spec v1.0

Hi All, Re-sending public review email of RISC-V Boot and Runtime Services Specification. Please see

Jun 20

Jun 17

Public review of Svrsw60t59b Standard Extension

Greetings! We are delighted to announce the commencement of the public review period for the

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Public review of Svrsw60t59b Standard Extension

Greetings! We are delighted to announce the commencement of the public review period for the

Jun 17

Jun 9

Public Review : RISC-V Supervisor Binary Interface (SBI) version v3.0

Hi All, The review period is now officially closed. We appreciate your participation in the review

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Public Review : RISC-V Supervisor Binary Interface (SBI) version v3.0

Hi All, The review period is now officially closed. We appreciate your participation in the review

Jun 9

Me, Andrew Jones2

Jun 4

Public Review of SBI 3.0.-rc7 : Suggested changes for SBI version: 3.0-rc7 draft - TJS 1

On Sat, May 24, 2025 at 12:50:44AM -0700, Me wrote: > Chapter 5: > > Page 17: > > The

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Public Review of SBI 3.0.-rc7 : Suggested changes for SBI version: 3.0-rc7 draft - TJS 1

On Sat, May 24, 2025 at 12:50:44AM -0700, Me wrote: > Chapter 5: > > Page 17: > > The

Jun 4

Michael Clark, … MitchAlsup20

May 8

a super regular RISC that encodes constants in immediate blocks.

On Friday, 9 May 2025 at 11:39:32 UTC+12 MitchAlsup wrote: Also note:: if you have a convenient bit-

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a super regular RISC that encodes constants in immediate blocks.

On Friday, 9 May 2025 at 11:39:32 UTC+12 MitchAlsup wrote: Also note:: if you have a convenient bit-

May 8

Vadím Sukhomlínov, … MitchAlsup72

Apr 28

Add with carry instructions

I should mention that several of the carries are performed improperly. On Sunday, April 27, 2025 at 3

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Add with carry instructions

I should mention that several of the carries are performed improperly. On Sunday, April 27, 2025 at 3

Apr 28

Ved Shanbhogue2

Apr 21

Public review of Non-leaf PTE invalidation and Address range invalidation extensions

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

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Public review of Non-leaf PTE invalidation and Address range invalidation extensions

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

Apr 21

Adnan Hamid, … Allen Baum30

Apr 11

MUST software mark unsued PTEs in a page directory as not valid ?

That is an microarchitectural fix for this issue - but is implicitly allowed by the architecture, as

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MUST software mark unsued PTEs in a page directory as not valid ?

That is an microarchitectural fix for this issue - but is implicitly allowed by the architecture, as

Apr 11

Allen Baum, Greg Favor6

Apr 9

memory mapped control registers

On Wed, Apr 9, 2025, 12:15 PM Allen Baum <allen...@esperantotech.com> wrote: Maybe my

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memory mapped control registers

On Wed, Apr 9, 2025, 12:15 PM Allen Baum <allen...@esperantotech.com> wrote: Maybe my

Apr 9

Mar 4

BDEP & BEXT instruction in RISC-V

Greetings everyone, We've been working on optimizing RISC-V for big data tools like Spark and

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BDEP & BEXT instruction in RISC-V

Greetings everyone, We've been working on optimizing RISC-V for big data tools like Spark and

Mar 4

Adnan Hamid, … Greg Favor9

Mar 3

may cbo.flush on non-cacheable memory raise an exception ?

Hi Greg, Got it. Where should such questions requesting clarification of the specification from

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may cbo.flush on non-cacheable memory raise an exception ?

Hi Greg, Got it. Where should such questions requesting clarification of the specification from

Mar 3

Jan 23

Misc/RFC: Changing encoding for my jumbo-prefix extension...

After thinking some, I decided to change the scheme I was using for encoding jumbo prefixes in my

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Misc/RFC: Changing encoding for my jumbo-prefix extension...

After thinking some, I decided to change the scheme I was using for encoding jumbo prefixes in my

Jan 23

Sunil V L, Heinrich Schuchardt5

Jan 14

Public Review of the ACPI RISC-V IO Mapping Table (RIMT) Specification

On Tue, Jan 14, 2025 at 02:17:37PM +0100, Heinrich Schuchardt wrote: > On 14.01.25 13:52, Sunil VL

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Public Review of the ACPI RISC-V IO Mapping Table (RIMT) Specification

On Tue, Jan 14, 2025 at 02:17:37PM +0100, Heinrich Schuchardt wrote: > On 14.01.25 13:52, Sunil VL

Jan 14

Ved Shanbhogue3

12/21/24

Public Review of the RISC-V Server SoC Specification

Greetings ! The review period for the RISC-V Server SoC Specification has concluded. Feedback

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Public Review of the RISC-V Server SoC Specification

Greetings ! The review period for the RISC-V Server SoC Specification has concluded. Feedback

12/21/24

Christian Herber, … BGB10

12/13/24

Public review for standard extensions Zilsd & Zclsd

The public review is complete. Thanks to everybody who participated. The following were the primary

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Public review for standard extensions Zilsd & Zclsd

The public review is complete. Thanks to everybody who participated. The following were the primary

12/13/24

L Peter Deutsch, … Bruce Hoult5

12/6/24

Reading spec-in-development docs

https://github.com/riscv/riscv-dot-product/releases/download/v0.0.1/dot-product.pdf On Sat, Dec 7,

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Reading spec-in-development docs

https://github.com/riscv/riscv-dot-product/releases/download/v0.0.1/dot-product.pdf On Sat, Dec 7,

12/6/24

L Peter Deutsch, BGB2

12/3/24

Compiler impact of RVA20/22/23U64 adoption

On 12/3/2024 12:27 PM, L Peter Deutsch wrote: > I'm writing a compiler one of whose targets is

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Compiler impact of RVA20/22/23U64 adoption

On 12/3/2024 12:27 PM, L Peter Deutsch wrote: > I'm writing a compiler one of whose targets is

12/3/24

11/17/24

How to skip Vector extension (v) when building riscv-tests?

Hi, experts: I did not include Vector extension (v) when building my RISC-V GNU toolchain; the ISA is

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How to skip Vector extension (v) when building riscv-tests?

Hi, experts: I did not include Vector extension (v) when building my RISC-V GNU toolchain; the ISA is

11/17/24

Robert Finch, … BGB7

11/8/24

Architecture CALL / RETURN instructions

On 11/8/2024 11:40 AM, Robert Lipe wrote: > Since this is inherently quite specific to your

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Architecture CALL / RETURN instructions

On 11/8/2024 11:40 AM, Robert Lipe wrote: > Since this is inherently quite specific to your

11/8/24

Kito Cheng, … Kito Cheng5

11/7/24

Public review for Non-ISA Specification: RISC-V vector intrinsic

Hi BGB: Thanks so much for your detailed response! Let me address your points one by one: - Why are

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Public review for Non-ISA Specification: RISC-V vector intrinsic

Hi BGB: Thanks so much for your detailed response! Let me address your points one by one: - Why are

11/7/24

Anup Patel, … kr...@sifive.com13

10/14/24

Re: Comment on: RISC-V Semihosting specification

I was reacting to Bruce's suggestion to add a new ebreak. I agree it would be useful to add a

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Re: Comment on: RISC-V Semihosting specification

I was reacting to Bruce's suggestion to add a new ebreak. I agree it would be useful to add a

10/14/24

Nasir Abbas, … Al Martin4

10/9/24

FPU implementation

Based on personal experience, you should be able to get close to your goals using HardFloat as your

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FPU implementation

Based on personal experience, you should be able to get close to your goals using HardFloat as your

10/9/24

Nasir Abbas, … Bruce Hoult3

10/7/24

It uses 4 cycles per instruction, so clearly not. On Tue, Oct 8, 2024 at 5:30 AM Nasir Abbas <

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It uses 4 cycles per instruction, so clearly not. On Tue, Oct 8, 2024 at 5:30 AM Nasir Abbas <

10/7/24

10/7/24

RVA23/RVB23 public review feedback and responses

Public review has closed on the RVA23 and RVB23 profiles. The following were the primary issues

unread,

RVA23/RVB23 public review feedback and responses

Public review has closed on the RVA23 and RVB23 profiles. The following were the primary issues

10/7/24

Nasir Abbas, Tommy Murphy2

10/7/24

Duplicate post? > Hi everyone can someone tell me that the PicoRV-32 core is pipelined. I don'

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Duplicate post? > Hi everyone can someone tell me that the PicoRV-32 core is pipelined. I don'

10/7/24

10/4/24

Summary of Privileged Architecture version 1.13 public review feedback

Public review of "Priv 1.13" - namely the Machine-Level ISA version 1.13 (aka Sm1p13) and

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Summary of Privileged Architecture version 1.13 public review feedback

Public review of "Priv 1.13" - namely the Machine-Level ISA version 1.13 (aka Sm1p13) and

10/4/24

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