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RISC-V ISA Dev

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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.

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Jerry Ho, … Jeff Scott22

10/28/21

question on NMI

Thanks Tommy! That was very helpful and is along the same lines I would take if doing this as a

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question on NMI

Thanks Tommy! That was very helpful and is along the same lines I would take if doing this as a

10/28/21

7/6/20

Understand the custom instruction

Hi experties ..! I am trying to understand custom instruction added using a python script for orca(

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Understand the custom instruction

Hi experties ..! I am trying to understand custom instruction added using a python script for orca(

7/6/20

Sourav Roy, … Jeff Scott12

6/25/20

Delegation of machine mode interrupts

Thanks, this is clear. Jeff From: Andrew Waterman <wate...@eecs.berkeley.edu> Sent: Wednesday,

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Delegation of machine mode interrupts

Thanks, this is clear. Jeff From: Andrew Waterman <wate...@eecs.berkeley.edu> Sent: Wednesday,

6/25/20

View more pinned conversations

3:02 AM

Question about sparse format choice for RVV-accelerated SpMV

Hi everyone, I had another question while thinking about sparse matrix formats for RVV-targeted SpMV

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Question about sparse format choice for RVV-accelerated SpMV

Hi everyone, I had another question while thinking about sparse matrix formats for RVV-targeted SpMV

3:02 AM

Yash Kaushik, Jash Ambaliya2

2:30 AM

Question about zero handling in CSR compression

In most production sparse libraries, the conversion routine usually does not apply an implicit

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Question about zero handling in CSR compression

In most production sparse libraries, the conversion routine usually does not apply an implicit

2:30 AM

Apr 9

Fwd: [RISC-V tech-announce] Public Review: RISC-V Quality of Service Controllers Table (RQSC) Specification

Forwarding the Public Review Announcement on behalf of the original sender. ---------- Forwarded

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Fwd: [RISC-V tech-announce] Public Review: RISC-V Quality of Service Controllers Table (RQSC) Specification

Forwarding the Public Review Announcement on behalf of the original sender. ---------- Forwarded

Apr 9

Anirudh Kaushik, Greg Favor2

Mar 17

Question on constrained LR/SC loop properties

It is referring to the actual instruction sequence that is executed between an LR and paired SC. This

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Question on constrained LR/SC loop properties

It is referring to the actual instruction sequence that is executed between an LR and paired SC. This

Mar 17

Kevin Cameron, L Peter Deutsch2

Mar 17

Linker editing for processor extensions (ISA spec/use)

> rewrite the binary: Reed Hastings' former (?) company, whose name I don't remember at

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Linker editing for processor extensions (ISA spec/use)

> rewrite the binary: Reed Hastings' former (?) company, whose name I don't remember at

Mar 17

Trần Thế Hảo, Rafael Sene2

Mar 17

Sharing my MIPS JAL/JR Flow Visualization project

@Trần Thế Hảo You can open an issue to list it at https://github.com/riscv/learn. Atenciosamente |

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Sharing my MIPS JAL/JR Flow Visualization project

@Trần Thế Hảo You can open an issue to list it at https://github.com/riscv/learn. Atenciosamente |

Mar 17

Mar 11

Public Review of the RISC-V Server Platform Specification

Greetings! The review period has concluded. We greatly appreciate your participation in the review

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Public Review of the RISC-V Server Platform Specification

Greetings! The review period has concluded. We greatly appreciate your participation in the review

Mar 11

Mar 11

RFC: Sovereign Lock Architectural Logic for 3nm Nodes (Cross-referenced with OCP #840)

Hi Team, presenting a physical-layer logic for power control/security in 3nm nodes. Already archived

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RFC: Sovereign Lock Architectural Logic for 3nm Nodes (Cross-referenced with OCP #840)

Hi Team, presenting a physical-layer logic for power control/security in 3nm nodes. Already archived

Mar 11

王毛, … Kevin Cameron3

Mar 5

[PROPOSAL] Zps: A New Extension for Physical Sovereignty via $3 \to M2 \to 3$ Forksheet Intercepts

This is in the land of PUFs, root-of-trust and encryption keys. There has been considerable

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[PROPOSAL] Zps: A New Extension for Physical Sovereignty via $3 \to M2 \to 3$ Forksheet Intercepts

This is in the land of PUFs, root-of-trust and encryption keys. There has been considerable

Mar 5

Mar 2

Public Review Announcement: Instruction/Data Coherence and Consistency Extension (Ziccid)

PDF was left behind… it is attached now. Atenciosamente | Sincerely Rafael Peria de Sene Technical

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Public Review Announcement: Instruction/Data Coherence and Consistency Extension (Ziccid)

PDF was left behind… it is attached now. Atenciosamente | Sincerely Rafael Peria de Sene Technical

Mar 2

Trần Thế Hảo

Feb 14

Mips - Jal & Ra - Flow Process Application - RISC-V

https://claude.ai/public/artifacts/ea9a8c7a-d64e-4bac-84c9-ce51bf90729c MIPS JAL/JR Flow

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Mips - Jal & Ra - Flow Process Application - RISC-V

https://claude.ai/public/artifacts/ea9a8c7a-d64e-4bac-84c9-ce51bf90729c MIPS JAL/JR Flow

Feb 14

L Peter Deutsch, Bill Traynor3

Jan 25

Organizational improvements for current (20250508) ratified unprivileged ISA spec

> Thanks Peter, may I suggest a process to move your requested changes forward? Sorry, of course I

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Organizational improvements for current (20250508) ratified unprivileged ISA spec

> Thanks Peter, may I suggest a process to move your requested changes forward? Sorry, of course I

Jan 25

L Peter Deutsch, … BGB6

Jan 10

Calling convention for RV32_Zdinx

On 1/10/2026 2:17 PM, K. York wrote: > Once you have such a specification, it's really easy to

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Calling convention for RV32_Zdinx

On 1/10/2026 2:17 PM, K. York wrote: > Once you have such a specification, it's really easy to

Jan 10

12/23/25

GLYPH ISA update and a reflection on "metacognition"

Hi Folks, a year 2025 closing update on the GLYPH ISA, plus some reflection: latest: https://

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GLYPH ISA update and a reflection on "metacognition"

Hi Folks, a year 2025 closing update on the GLYPH ISA, plus some reflection: latest: https://

12/23/25

12/21/25

Misc: Tweak for usefulness of large instruction encodings?...

On 12/19/2025 6:28 PM, BGB wrote: > Thought: > Would keep the existing scheme for 16/32/48/64

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Misc: Tweak for usefulness of large instruction encodings?...

On 12/19/2025 6:28 PM, BGB wrote: > Thought: > Would keep the existing scheme for 16/32/48/64

12/21/25

sven boertjens, … Earl Killian26

12/5/25

Proposal for a consumer baseline profile between RV64GC and RVA23

Right, and RISC-V Vector is our SIMD, so it is basically required. I think you could argue whether

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Proposal for a consumer baseline profile between RV64GC and RVA23

Right, and RISC-V Vector is our SIMD, so it is basically required. I think you could argue whether

12/5/25

Vadím Sukhomlínov, … Al Martin8

10/3/25

When ternary `cmov` got removed from -Zb?

Al, thanks for the tip - indeed looks like CMOV is in the scope for the Scalar Efficiency SIG: https:

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When ternary `cmov` got removed from -Zb?

Al, thanks for the tip - indeed looks like CMOV is in the scope for the Scalar Efficiency SIG: https:

10/3/25

L Peter Deutsch, … BGB10

9/20/25

Comments on Zibi 0.1

On 9/19/2025 4:16 AM, Kevin Cameron wrote: > At OCP we discuss how to deploy a range of processors

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Comments on Zibi 0.1

On 9/19/2025 4:16 AM, Kevin Cameron wrote: > At OCP we discuss how to deploy a range of processors

9/20/25

7/23/25

Public Review: Zalasr (Load-Acquire Store-Release)

Greetings! On behalf of the author of this specification, we are forwarding this public review

unread,

Public Review: Zalasr (Load-Acquire Store-Release)

Greetings! On behalf of the author of this specification, we are forwarding this public review

7/23/25

7/21/25

Re: [RISC-V][tech-brs] Public Review of the RISC-V Boot and Runtime Services (BRS) spec v1.0

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

unread,

Re: [RISC-V][tech-brs] Public Review of the RISC-V Boot and Runtime Services (BRS) spec v1.0

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

7/21/25

Ved Shanbhogue2

7/18/25

Public review of Svrsw60t59b Standard Extension

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

unread,

Public review of Svrsw60t59b Standard Extension

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

7/18/25

7/18/25

Re: [RISC-V tech-announce] Public review of Svrsw60t59b Standard Extension

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

unread,

Re: [RISC-V tech-announce] Public review of Svrsw60t59b Standard Extension

Greetings ! The review period has concluded. We greatly appreciate your participation in the review

7/18/25

Shreyas Talwekar

7/7/25

RISC-V vs C Code Comparison for Simple Multiply and Accumulate (MAC) Operation

Hi, We tried profiling a simple MAC operation using both RISC-V Vector (RVV) intrinsics and plain C

unread,

RISC-V vs C Code Comparison for Simple Multiply and Accumulate (MAC) Operation

Hi, We tried profiling a simple MAC operation using both RISC-V Vector (RVV) intrinsics and plain C

7/7/25

Paris Oplopoios

7/3/25

Extension for overflow calculation?

Hello, Emulating x86 or AArch64 on RISC-V requires emulating the flags using multiple instructions.

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Extension for overflow calculation?

Hello, Emulating x86 or AArch64 on RISC-V requires emulating the flags using multiple instructions.

7/3/25

Oleksii Kurochko

6/25/25

Call of hfence_gvma_all after update of CSR_HGATP

Hello Community, I decided to check how KVM determines a length of VMIDLEN and found the following:

unread,

Call of hfence_gvma_all after update of CSR_HGATP

Hello Community, I decided to check how KVM determines a length of VMIDLEN and found the following:

6/25/25

Leyfoon Tan, … Allen Baum6

6/20/25

RE: Public Review for RPMI Specification

Hi all, We're pleased to announce that the latest version of the RPMI specification (v0.99) is

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RE: Public Review for RPMI Specification

Hi all, We're pleased to announce that the latest version of the RPMI specification (v0.99) is

6/20/25

6/20/25

Re: [RISC-V tech-announce] Public Review of the RISC-V Boot and Runtime Services (BRS) spec v1.0

Hi All, Re-sending public review email of RISC-V Boot and Runtime Services Specification. Please see

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Re: [RISC-V tech-announce] Public Review of the RISC-V Boot and Runtime Services (BRS) spec v1.0

Hi All, Re-sending public review email of RISC-V Boot and Runtime Services Specification. Please see

6/20/25

6/9/25

Public Review : RISC-V Supervisor Binary Interface (SBI) version v3.0

Hi All, The review period is now officially closed. We appreciate your participation in the review

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Public Review : RISC-V Supervisor Binary Interface (SBI) version v3.0

Hi All, The review period is now officially closed. We appreciate your participation in the review

6/9/25

Me, Andrew Jones2

6/4/25

Public Review of SBI 3.0.-rc7 : Suggested changes for SBI version: 3.0-rc7 draft - TJS 1

On Sat, May 24, 2025 at 12:50:44AM -0700, Me wrote: > Chapter 5: > > Page 17: > > The

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Public Review of SBI 3.0.-rc7 : Suggested changes for SBI version: 3.0-rc7 draft - TJS 1

On Sat, May 24, 2025 at 12:50:44AM -0700, Me wrote: > Chapter 5: > > Page 17: > > The

6/4/25

Michael Clark, … MitchAlsup20

5/8/25

a super regular RISC that encodes constants in immediate blocks.

On Friday, 9 May 2025 at 11:39:32 UTC+12 MitchAlsup wrote: Also note:: if you have a convenient bit-

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a super regular RISC that encodes constants in immediate blocks.

On Friday, 9 May 2025 at 11:39:32 UTC+12 MitchAlsup wrote: Also note:: if you have a convenient bit-

5/8/25

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