RISC-V ISA Dev

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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.

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Abhav S Velidi., Tommy Murphy2

10:32 AM

Implemetation of CSR (Machine Mode) as a beginner

Maybe looking at some of the existing open-source RISC-V implementations might help? From: 'Abhav

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Implemetation of CSR (Machine Mode) as a beginner

Maybe looking at some of the existing open-source RISC-V implementations might help? From: 'Abhav

10:32 AM

Anders Lindgren, … Earl Killian4

May 27

Feedback from IAR of the Zfa RISC-V extension

On 5/26/23 07:26, Anders Lindgren wrote: - The constants selected for FLI.i doesn't seem to match

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Feedback from IAR of the Zfa RISC-V extension

On 5/26/23 07:26, Anders Lindgren wrote: - The constants selected for FLI.i doesn't seem to match

May 27

jagten leo, MitchAlsup5

May 25

The hardware implementation of Atomic instruction in RISCV and performance differences compared to HTM

Thanks a lot! 'MitchAlsup' via RISC-V ISA Dev <isa...@groups.riscv.org> 于2023年5月26日周五

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The hardware implementation of Atomic instruction in RISCV and performance differences compared to HTM

Thanks a lot! 'MitchAlsup' via RISC-V ISA Dev <isa...@groups.riscv.org> 于2023年5月26日周五

May 25

Derek Hower, … Bruce Hoult6

May 18

Qualcomm feedback on Zicond

In C terms, the Elvis operator is x ? x : y except that x is only evaluated once. Both gcc (since

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Qualcomm feedback on Zicond

In C terms, the Elvis operator is x ? x : y except that x is only evaluated once. Both gcc (since

May 18

Anders Lindgren, … Bruce Hoult36

May 10

Feedback from IAR on the Zicond RISC-V extension

On Thu, May 11, 2023 at 11:56 AM Paul Campbell <tan...@gmail.com> wrote: I think it's

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Feedback from IAR on the Zicond RISC-V extension

On Thu, May 11, 2023 at 11:56 AM Paul Campbell <tan...@gmail.com> wrote: I think it's

May 10

Krste Asanovic, … Andrew Waterman10

May 4

Public review of Zfa Standard Extension for Additional Floating-Point Instructions

I don't disagree with the value of a "Zfainx" extension. However, at this stage in

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Public review of Zfa Standard Extension for Additional Floating-Point Instructions

I don't disagree with the value of a "Zfainx" extension. However, at this stage in

May 4

Krste Asanovic, … Andrea Parri7

Apr 26

Re: Public review of RISC-V Zicond conditional zeroing extension

> These are register-to-register instructions, so memory-ordering semantics > between HARTs are

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Re: Public review of RISC-V Zicond conditional zeroing extension

> These are register-to-register instructions, so memory-ordering semantics > between HARTs are

Apr 26

Anoop Mysore, … Tommy Thorn12

Apr 24

Thanks for mentioning Dromajo. It's been extensively verified (and the very many bug fixes is one

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Thanks for mentioning Dromajo. It's been extensively verified (and the very many bug fixes is one

Apr 24

Jim Kenua, … Tim Newsome5

Apr 20

RISC-V - Function like representation of Instructions

When I need this kind of info, I look at spike: https://github.com/riscv-software-src/riscv-isa-sim/

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RISC-V - Function like representation of Instructions

When I need this kind of info, I look at spike: https://github.com/riscv-software-src/riscv-isa-sim/

Apr 20

Rajeev Kumar, … Mark Hill6

Apr 17

Cycle approximate simulation

Hi Rajeev, If you are interested in CA models I would suggest joining the Performance Modelling SIG (

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Cycle approximate simulation

Hi Rajeev, If you are interested in CA models I would suggest joining the Performance Modelling SIG (

Apr 17

崔鲁平, Kelvin Goveas2

Apr 3

confuse about the two stage address translation in Hypervisor Extension

Hi Luping, For (2), if vsatp.mode=Sv39 and hgatp.mode=Sv39x4, the GPA that is input into the 2nd

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confuse about the two stage address translation in Hypervisor Extension

Hi Luping, For (2), if vsatp.mode=Sv39 and hgatp.mode=Sv39x4, the GPA that is input into the 2nd

Apr 3

Mar 30

Public review for non-ISA RISC-V IOMMU specification

Greetings! We are delighted to announce the start of the public review period for the following

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Public review for non-ISA RISC-V IOMMU specification

Greetings! We are delighted to announce the start of the public review period for the following

Mar 30

Juha Manninen, … MitchAlsup23

Mar 29

RISC-V macro operation fusion + out of order execution

Sorry for the length of the reply:: On Saturday, March 4, 2023 at 7:37:51 PM UTC-6 L Peter Deutsch

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RISC-V macro operation fusion + out of order execution

Sorry for the length of the reply:: On Saturday, March 4, 2023 at 7:37:51 PM UTC-6 L Peter Deutsch

Mar 29

Ahsan Ali, … Palmer Dabbelt5

Feb 28

Pre-amption in RISC-V PLIC

On Mon, 27 Feb 2023 01:29:03 PST (-0800), 2019...@gmail.com wrote: > Can we have support of that

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Pre-amption in RISC-V PLIC

On Mon, 27 Feb 2023 01:29:03 PST (-0800), 2019...@gmail.com wrote: > Can we have support of that

Feb 28

Andrew Waterman, … Allen Baum22

Feb 28

Public review of Fast Track extension Zihintntl

The architectural complexity of this has been carefully minimized by the precise semantics of the

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Public review of Fast Track extension Zihintntl

The architectural complexity of this has been carefully minimized by the precise semantics of the

Feb 28

Jeff Scott, … MitchAlsup65

Feb 13

Only 16b instructions RISC-V

On Monday, February 13, 2023 at 2:07:23 AM UTC-6 BGB wrote: On 2/12/2023 10:28 PM, Shumpei Kawasaki

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Only 16b instructions RISC-V

On Monday, February 13, 2023 at 2:07:23 AM UTC-6 BGB wrote: On 2/12/2023 10:28 PM, Shumpei Kawasaki

Feb 13

Mathan Kumar, Tommy Murphy5

Feb 8

qemu emulation of RISC V sifive Hifive unleashed

Cool, thanks! On Wed, 8 Feb 2023 at 14:55, Tommy Murphy <tommy_...@hotmail.com> wrote: What

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qemu emulation of RISC V sifive Hifive unleashed

Cool, thanks! On Wed, 8 Feb 2023 at 14:55, Tommy Murphy <tommy_...@hotmail.com> wrote: What

Feb 8

Rajeev Kumar, … MitchAlsup5

Feb 7

API for internal state

Not really trying to answer his question, as to point out how hard it would be to answer his question

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API for internal state

Not really trying to answer his question, as to point out how hard it would be to answer his question

Feb 7

Feb 7

Alternative RV128 CLARIFICATION: registers are 16x64b+16x[64b or 128b]

Hi, some of the comments I got about yesterday's post ("Alternative RV128: 16x 64b + 16x

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Alternative RV128 CLARIFICATION: registers are 16x64b+16x[64b or 128b]

Hi, some of the comments I got about yesterday's post ("Alternative RV128: 16x 64b + 16x

Feb 7

Xan Phung, … BGB4

Feb 7

Alternative RV128: 16x 64b + 16x 128b registers are better than 32x 128b

Hi Allen, Thanks for your constructive questions, which I appreciated - as they demonstrated

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Alternative RV128: 16x 64b + 16x 128b registers are better than 32x 128b

Hi Allen, Thanks for your constructive questions, which I appreciated - as they demonstrated

Feb 7

Xan Phung, … MitchAlsup5

Feb 6

Proposal: Alternative RV128 (Upgrade path for Legacy 64b systems, skipping RV64 entirely)

On Sunday, February 5, 2023 at 10:55:23 PM UTC-6 Xan Phung wrote: Hi Mitch, thanks for your comments

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Proposal: Alternative RV128 (Upgrade path for Legacy 64b systems, skipping RV64 entirely)

On Sunday, February 5, 2023 at 10:55:23 PM UTC-6 Xan Phung wrote: Hi Mitch, thanks for your comments

Feb 6

Michael Zoran, … Tommy Murphy9

Jan 28

Processors that implement Svpbmt

As far as I know, it doesn't. The in development Hifive Pro from sifive apparently does. On

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Processors that implement Svpbmt

As far as I know, it doesn't. The in development Hifive Pro from sifive apparently does. On

Jan 28

Kokolakis, Georgios, … Allen Baum4

Jan 26

timeline for "PMP Enhancements for memory access and execution prevention on Machine mode"

This is a ratified *extension*, and that means it is official, regardless of whether it is currently

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timeline for "PMP Enhancements for memory access and execution prevention on Machine mode"

This is a ratified *extension*, and that means it is official, regardless of whether it is currently

Jan 26

Jan 24

Public review for Zvfh/Zvfhmin

We are delighted to announce the start of the public review period for the following proposed

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Public review for Zvfh/Zvfhmin

We are delighted to announce the start of the public review period for the following proposed

Jan 24

akhilesh Kotwaliwale, … Tommy Murphy16

Jan 17

RV32E toolchain

Yes i did. And I have icarus verilog version 10.1 On Tuesday, 17 January 2023 at 15:23:42 UTC+5:30

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RV32E toolchain

Yes i did. And I have icarus verilog version 10.1 On Tuesday, 17 January 2023 at 15:23:42 UTC+5:30

Jan 17

Robert Lipe, … Tommy Murphy12

Jan 16

Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 5 updates in 1 topic

On Mon, Jan 16, 2023 at 4:09 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Thanks for the

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Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 5 updates in 1 topic

On Mon, Jan 16, 2023 at 4:09 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Thanks for the

Jan 16

Jan Oleksiewicz

Jan 8

XTightlyCoupledIO

Hi isa-dev Recently I have made a new custom extension providing avr8/PRU like IO instructions. https

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XTightlyCoupledIO

Hi isa-dev Recently I have made a new custom extension providing avr8/PRU like IO instructions. https

Jan 8

Ruslan Nikolaev, … MitchAlsup11

Jan 5

128-bit CAS for RISC V

On Thursday, January 5, 2023 at 3:18:12 AM UTC-6 acahalan wrote: On 1/4/23, 'MitchAlsup' via

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128-bit CAS for RISC V

On Thursday, January 5, 2023 at 3:18:12 AM UTC-6 acahalan wrote: On 1/4/23, 'MitchAlsup' via

Jan 5

Olof Kindgren, … Robert Lipe21

Jan 5

Thoughts on a Zrfinram extension

On Thu, Jan 5, 2023 at 8:28 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Apologies if

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Thoughts on a Zrfinram extension

On Thu, Jan 5, 2023 at 8:28 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Apologies if

Jan 5

Amr Zaky, … Rishiyur Nikhil3

12/27/22

Formal Spec for RISC V

Yes, there is a formal spec for the Unprivileged RV32/64 IMAFDC and Privileged RISC-V ISAs. The spec

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Formal Spec for RISC V

Yes, there is a formal spec for the Unprivileged RV32/64 IMAFDC and Privileged RISC-V ISAs. The spec

12/27/22

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