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RISC-V ISA Dev
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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.
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Boul chandra Garai
, …
Tommy Murphy
19
Jun 30
Building/installing riscv-spike simulator with vector extension
> Could you guide me for the riscv-llvm building See here: * https://github.com/riscv-collab/riscv
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Building/installing riscv-spike simulator with vector extension
> Could you guide me for the riscv-llvm building See here: * https://github.com/riscv-collab/riscv
Jun 30
Michael Clark
3
Jun 20
RISC-IB - a super regular RISC with immediate blocks
On 6/21/24 11:26, Michael Clark wrote: > IBS is a branch instruction for the constant stream. near
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RISC-IB - a super regular RISC with immediate blocks
On 6/21/24 11:26, Michael Clark wrote: > IBS is a branch instruction for the constant stream. near
Jun 20
Wei Wu (吴伟)
Jun 2
Fwd: RISC-V Summit China 2024: The call for speakers and sponsorship packages have been announced.
Please note that the submission deadline is June 22 AoE. Any RISC-V related topics are welcome! -----
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Fwd: RISC-V Summit China 2024: The call for speakers and sponsorship packages have been announced.
Please note that the submission deadline is June 22 AoE. Any RISC-V related topics are welcome! -----
Jun 2
Ved Shanbhogue
2
May 30
Public review for Double Trap standard extension
Greetings ! The review period for the Smdbltrp/Ssdbltrp standard extensions concluded on May 29. We
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Public review for Double Trap standard extension
Greetings ! The review period for the Smdbltrp/Ssdbltrp standard extensions concluded on May 29. We
May 30
Martin Maas
May 28
Re: Public Review for RISC-V Pointer Masking Specification
The public review period for the RISC-V Pointer Masking Specification concluded on April 19. The
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Re: Public Review for RISC-V Pointer Masking Specification
The public review period for the RISC-V Pointer Masking Specification concluded on April 19. The
May 28
Oleksii Kurochko
May 28
HVIP and related registers usage
Hello @everyone, I would like to ask about the HVIP register and its usage. In the specification, it
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HVIP and related registers usage
Hello @everyone, I would like to ask about the HVIP register and its usage. In the specification, it
May 28
san zhang
, …
Allen Baum
6
May 27
Can risc-v processors perform speculative instruction fetches in MMIO space?
Thank you very much for all the responses. The answers provided by Greg Favor and Allen Baum have
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Can risc-v processors perform speculative instruction fetches in MMIO space?
Thank you very much for all the responses. The answers provided by Greg Favor and Allen Baum have
May 27
JAYANTH R
, …
Allen Baum
4
May 14
breakpoint exception and mret
Your questions are a bit ambiguous. Yes, eBreak will cause a trap with the cause set to eBreak, and
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breakpoint exception and mret
Your questions are a bit ambiguous. Yes, eBreak will cause a trap with the cause set to eBreak, and
May 14
Tommy Murphy
May 13
Confused about authoritative specification info
I'm very confused about the following three issues - maybe somebody can help to elucidate? Thanks
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Confused about authoritative specification info
I'm very confused about the following three issues - maybe somebody can help to elucidate? Thanks
May 13
Ved Shanbhogue
May 1
Greetings! We are delighted to announce the commencement of the public review period for the Double
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Greetings! We are delighted to announce the commencement of the public review period for the Double
May 1
Georgios Christou
Apr 29
Public review ended for Zicfilp and Zicfiss extensions.
Greetings! The review period for Zicfiss and Zicfilp extension spec. concluded on April 27. During
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Public review ended for Zicfilp and Zicfiss extensions.
Greetings! The review period for Zicfiss and Zicfilp extension spec. concluded on April 27. During
Apr 29
Jan Gray
Apr 25
introducing Composable Extensions, and invitation to participate
Greetings. The Soft CPU SIG was formed in 2019 to advance RISC-V for FPGA SoCs, and on behalf of RISC
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introducing Composable Extensions, and invitation to participate
Greetings. The Soft CPU SIG was formed in 2019 to advance RISC-V for FPGA SoCs, and on behalf of RISC
Apr 25
Jeff Scheel
Apr 19
Re: [RISC-V] [tech-privileged] Comments re {priv,unpriv}-isa-asciidoc-20240411.pdf
Hi, David, I'm sorry you had a problem. But, the issue is not that the group has been archived,
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Re: [RISC-V] [tech-privileged] Comments re {priv,unpriv}-isa-asciidoc-20240411.pdf
Hi, David, I'm sorry you had a problem. But, the issue is not that the group has been archived,
Apr 19
Rohan Ahmed
, …
Bruce Hoult
8
Apr 18
Bit Manipulation C code style testing
Thanks to all of you for giving your insights. BR, Rohan On Thursday, April 18, 2024 at 7:20:23 AM
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Bit Manipulation C code style testing
Thanks to all of you for giving your insights. BR, Rohan On Thursday, April 18, 2024 at 7:20:23 AM
Apr 18
Eric Shiu
2
Apr 12
Re: Public Review for RISC-V CBQRI and Ssqosid specifications
Greetings!The review period for the RISC-V CBQRI non-ISA specification and its related Ssqosid ISA
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Re: Public Review for RISC-V CBQRI and Ssqosid specifications
Greetings!The review period for the RISC-V CBQRI non-ISA specification and its related Ssqosid ISA
Apr 12
Robertson, Iain
Apr 10
Public Review for Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V specification
[3 rd attempt now that I have permission to post to ISA-Dev. With further apologies to those who
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Public Review for Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V specification
[3 rd attempt now that I have permission to post to ISA-Dev. With further apologies to those who
Apr 10
Ved Shanbhogue
2
Apr 9
Public review for Svvptc standard extension
Greetings ! The review period for the Svvptc standard extension concluded on April 8. We appreciate
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Public review for Svvptc standard extension
Greetings ! The review period for the Svvptc standard extension concluded on April 8. We appreciate
Apr 9
Ved Shanbhogue
2
Apr 5
Public Review for RISC-V RERI non-ISA specification
Greetings ! The review period for RISC-V RAS Error Record Register Interface (RERI) non-ISA
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Public Review for RISC-V RERI non-ISA specification
Greetings ! The review period for RISC-V RAS Error Record Register Interface (RERI) non-ISA
Apr 5
Georgios Christou
Mar 28
Public review for Zicfilp and Zicfiss extensions
Dear all, We are delighted to announce the public review for the Zicfilp and Zicfiss standard
unread,
Public review for Zicfilp and Zicfiss extensions
Dear all, We are delighted to announce the public review for the Zicfilp and Zicfiss standard
Mar 28
Ved Shanbhogue
Mar 28
Re: [RISC-V tech-announce] Public Review for Zaamo and Zalrsc Standard Extensions
Greetings ! The review period for Zaamo and Zalrsc concluded on March 27. During the review Anders
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Re: [RISC-V tech-announce] Public Review for Zaamo and Zalrsc Standard Extensions
Greetings ! The review period for Zaamo and Zalrsc concluded on March 27. During the review Anders
Mar 28
L Peter Deutsch
, …
Rafael Sene
4
Mar 26
New Jira spec interface; comment on Zilsp draft 0.8.1
> @Peter, I'm interested in learning about the steps you executed :) Could you > describe
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New Jira spec interface; comment on Zilsp draft 0.8.1
> @Peter, I'm interested in learning about the steps you executed :) Could you > describe
Mar 26
Ved Shanbhogue
2
Mar 23
Public Review for B Standard Extension
Greetings ! The review period for the B standard extension concluded on March 22. We appreciate your
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Public Review for B Standard Extension
Greetings ! The review period for the B standard extension concluded on March 22. We appreciate your
Mar 23
JAYANTH R
,
Tommy Murphy
2
Mar 22
Triggers (tselect and tdata1)
> 1) Can tselect and tdata1 triggers be accessed in u-mode? The debug spec Version 1.0.0-rc2 (
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Triggers (tselect and tdata1)
> 1) Can tselect and tdata1 triggers be accessed in u-mode? The debug spec Version 1.0.0-rc2 (
Mar 22
Martin Maas
Mar 20
Public Review for RISC-V Pointer Masking Specification
The RISC-V J Extension TG is delighted to announce the start of the public review period for the
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Public Review for RISC-V Pointer Masking Specification
The RISC-V J Extension TG is delighted to announce the start of the public review period for the
Mar 20
Andrew Waterman
Mar 19
Public review of Smrnmi (resumable non-maskable interrupts) extension
Hi folks, We're happy to announce that the Smrnmi extension for resumable non-maskable interrupts
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Public review of Smrnmi (resumable non-maskable interrupts) extension
Hi folks, We're happy to announce that the Smrnmi extension for resumable non-maskable interrupts
Mar 19
Ved Shanbhogue
Mar 7
Re: [RISC-V tech-announce] Public Review for Zabha Standard Extension
Greetings! The review period for the Zabha Fast Track Specification ended on March 6. During the
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Re: [RISC-V tech-announce] Public Review for Zabha Standard Extension
Greetings! The review period for the Zabha Fast Track Specification ended on March 6. During the
Mar 7
Ved Shanbhogue
,
BGB
4
Feb 27
Public Review for Zaamo and Zalrsc Standard Extensions
On 2/27/2024 4:00 PM, Ved Shanbhogue wrote: > BGB wrote: >> So, looks like taking the 'A
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Public Review for Zaamo and Zalrsc Standard Extensions
On 2/27/2024 4:00 PM, Ved Shanbhogue wrote: > BGB wrote: >> So, looks like taking the 'A
Feb 27
BGB
, …
Al Martin
15
Feb 13
Misc: Relative testing between RV64G and my own ISA.
On 2/13/2024 1:12 PM, Al Martin wrote: > Have you thought about /lowering /the frequency target?
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Misc: Relative testing between RV64G and my own ISA.
On 2/13/2024 1:12 PM, Al Martin wrote: > Have you thought about /lowering /the frequency target?
Feb 13
Robert Finch
Feb 13
arpl compiler
Got my arpl compiler to generate RISCV code. Bound to be lots of bugs yet. No assembler yet, but its
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arpl compiler
Got my arpl compiler to generate RISCV code. Bound to be lots of bugs yet. No assembler yet, but its
Feb 13
Adnan Hamid
,
Andrew Waterman
4
Feb 12
Possible specification typo for Sv57x4
A note for future readers: Working draft of the specification are at https://github.com/riscv/riscv-
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Possible specification typo for Sv57x4
A note for future readers: Working draft of the specification are at https://github.com/riscv/riscv-
Feb 12