RISC-V ISA Dev

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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.

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ariyosko, … BGB4

Aug 12

Hi. Regarding RISC-V Exceptions, Traps, interrupts and CSRs

On 8/12/2022 10:28 AM, ariyosko wrote: > Hi. > > I am very new to RISC-V and trying to write

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Hi. Regarding RISC-V Exceptions, Traps, interrupts and CSRs

On 8/12/2022 10:28 AM, ariyosko wrote: > Hi. > > I am very new to RISC-V and trying to write

Aug 12

Simon Jackson, MitchAlsup5

Aug 10

Code Data Isolation

Yep, it still needs some work. Not needing a coach integration, more of coverage security open

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Code Data Isolation

Yep, it still needs some work. Not needing a coach integration, more of coverage security open

Aug 10

cinco...@gmail.com, … MitchAlsup5

Aug 1

Invalid branch address exceptions

Adding:: When you transfer control due to a branch or jump and the Fetch address is ill-formed, the

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Invalid branch address exceptions

Adding:: When you transfer control due to a branch or jump and the Fetch address is ill-formed, the

Aug 1

Timothée ZERBIB

Jul 20

Question on interruption routing

Hi all, First of all, I am new on RISC-V and I would like to apologize if this question should have

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Question on interruption routing

Hi all, First of all, I am new on RISC-V and I would like to apologize if this question should have

Jul 20

Frédéric Pétrot, … Krste Asanovic3

Jul 18

Reserved opcodes in RVC, Quadrant 1

To make a stronger statement, don't try to predict use of any encodings until the specs are at

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Reserved opcodes in RVC, Quadrant 1

To make a stronger statement, don't try to predict use of any encodings until the specs are at

Jul 18

Kito Cheng, … Andrew Waterman8

Jul 15

Public review for Non-ISA Specification: psABI

Folks, chill. Liviu was just letting off some steam; we do care about and will eventually have an

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Public review for Non-ISA Specification: psABI

Folks, chill. Liviu was just letting off some steam; we do care about and will eventually have an

Jul 15

L Peter Deutsch, Jim Wilson2

Jul 14

Typo in psABI v1.0-rc3?

On Thu, Jul 14, 2022 at 12:55 PM L Peter Deutsch <ghost@major2nd.com> wrote: Section A.2, Linux

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Typo in psABI v1.0-rc3?

On Thu, Jul 14, 2022 at 12:55 PM L Peter Deutsch <ghost@major2nd.com> wrote: Section A.2, Linux

Jul 14

cinco...@gmail.com, … BGB14

Jul 11

should loads to reg 0 actually do the load? (but not write a reg)?

On 7/10/2022 11:22 PM, Allen Baum wrote: > So, you're not adding a custom extension to RV, you

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should loads to reg 0 actually do the load? (but not write a reg)?

On 7/10/2022 11:22 PM, Allen Baum wrote: > So, you're not adding a custom extension to RV, you

Jul 11

Ved Shanbhogue, … Simon Jackson5

Jul 8

Public review for standard extensions Zwrs

It could work for a lot of things when low power is required. For more general poling a cache-flush-

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Public review for standard extensions Zwrs

It could work for a lot of things when low power is required. For more general poling a cache-flush-

Jul 8

Jul 5

Question regarding VSEW restriction when vflmul < 1

Hi, For spike, the vill bit is set when “vsew > std::min(vflmul, 1.0f) * ELEN” (https://github.com

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Question regarding VSEW restriction when vflmul < 1

Hi, For spike, the vill bit is set when “vsew > std::min(vflmul, 1.0f) * ELEN” (https://github.com

Jul 5

Philipp Tomsich, … Palmer Dabbelt28

Jun 30

Re: [RFC] zicntr and zihpm issues and how to deal with future ISA spec changes in future?

On Thu, 30 Jun 2022 09:45:31 PDT (-0700), christoph.muellner@vrull.eu wrote: > Here is a quick

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Re: [RFC] zicntr and zihpm issues and how to deal with future ISA spec changes in future?

On Thu, 30 Jun 2022 09:45:31 PDT (-0700), christoph.muellner@vrull.eu wrote: > Here is a quick

Jun 30

Wei Wu (吴伟)

Jun 29

[CFP] Talk proposal submission for RISC-V Summit China 2022 is still open!

Hi all, There are 5 days remaining for submission. Hurry up! What is RISC-V Summit China 2022? ======

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[CFP] Talk proposal submission for RISC-V Summit China 2022 is still open!

Hi all, There are 5 days remaining for submission. Hurry up! What is RISC-V Summit China 2022? ======

Jun 29

Tor Jeremiassen, Nick Knight4

Jun 2

Vector Segment Load/Store Encoding

Yes, this is clarified in the last two paragraphs of Section 7.2: The nf[2:0] field encodes the

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Vector Segment Load/Store Encoding

Yes, this is clarified in the last two paragraphs of Section 7.2: The nf[2:0] field encodes the

Jun 2

David Weaver, … BGB3

Jun 2

"B" extension and misa register?

On 6/2/2022 11:19 AM, Greg Favor wrote: > On Thu, Jun 2, 2022 at 9:05 AM David Weaver <dweaver.

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"B" extension and misa register?

On 6/2/2022 11:19 AM, Greg Favor wrote: > On Thu, Jun 2, 2022 at 9:05 AM David Weaver <dweaver.

Jun 2

Robert Finch, … James Cloos13

May 27

Decimal Floating-point

btw, i suspect a more useful idea is to make L be the first extension to use 48bit ops. a 32bit chunk

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Decimal Floating-point

btw, i suspect a more useful idea is to make L be the first extension to use 48bit ops. a 32bit chunk

May 27

jc riscvproject

May 24

Cacheability in virtualized environment and cache control bits

Hi, I have 2 questions similar to this question from a few days ago regarding cacheability and cache

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Cacheability in virtualized environment and cache control bits

Hi, I have 2 questions similar to this question from a few days ago regarding cacheability and cache

May 24

Hyesoon Kim, … Abel Bernabeu8

May 20

How to propose a new SIMT (GPU) extension ISA?

Am happy to continue this conversation on: sig-graphics@riscv.org :-) We need more people with an

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How to propose a new SIMT (GPU) extension ISA?

Am happy to continue this conversation on: sig-graphics@riscv.org :-) We need more people with an

May 20

mzoran, Kelvin Goveas2

May 20

Cache control from VM page tables

Hi, I am not sure exactly what you mean by "data cache control" but the svpbmt extension

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Cache control from VM page tables

Hi, I am not sure exactly what you mean by "data cache control" but the svpbmt extension

May 20

KN Ganendra Murthy

Apr 27

Programming FPGA through RISC-V CPU

Hi all, I have a RISC-V CPU(SoC) based Hifive Sifive Unmatched Board.I am connecting Intel Arria 10

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Programming FPGA through RISC-V CPU

Hi all, I have a RISC-V CPU(SoC) based Hifive Sifive Unmatched Board.I am connecting Intel Arria 10

Apr 27

Brendan Bohannon, … Torbjørn Viem Ness50

Apr 15

Misc (Maybe controversial): Scaled Index Load/Store?

Zce is getting relatively close to stable now. I don't expect major changes to the instructions

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Misc (Maybe controversial): Scaled Index Load/Store?

Zce is getting relatively close to stable now. I don't expect major changes to the instructions

Apr 15

Hao Lee, Edwin Sutanto2

Apr 7

Question about memory ordering and barrier

let me try to explain, I just read the RVWMO myself because of OoO and A =/= B P0 P1 === === ld B

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Question about memory ordering and barrier

let me try to explain, I just read the RVWMO myself because of OoO and A =/= B P0 P1 === === ld B

Apr 7

Bernhard Schommer, … Nick Knight4

Mar 24

Clarification regarding NaN in fcvt instructions

Thanks for the clarification. Best, -Bernhard Nick Knight schrieb am Donnerstag, 24. März 2022 um 17:

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Clarification regarding NaN in fcvt instructions

Thanks for the clarification. Best, -Bernhard Nick Knight schrieb am Donnerstag, 24. März 2022 um 17:

Mar 24

Mar 23

Re: [RISC-V] [tech-unixplatformspec] Public review of RISC-V UEFI Protocol Specification

(Resending for RISC-V ISA-DEV and RISC-V SW-DEV because previous email was not received on these

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Re: [RISC-V] [tech-unixplatformspec] Public review of RISC-V UEFI Protocol Specification

(Resending for RISC-V ISA-DEV and RISC-V SW-DEV because previous email was not received on these

Mar 23

Karthik Punukollu, … Allen Baum8

Mar 16

which CSR holds current privilege mode ?

Thanks Allen and York for responses. Yes, I was planning to choose internal CSRs which are updated at

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which CSR holds current privilege mode ?

Thanks Allen and York for responses. Yes, I was planning to choose internal CSRs which are updated at

Mar 16

Feb 23

Re: [isa-dev] Conditional Branches Clarification

The manual is correct. "This is confusing to me because I would think a BLT instruction can be

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Re: [isa-dev] Conditional Branches Clarification

The manual is correct. "This is confusing to me because I would think a BLT instruction can be

Feb 23

cincocerros, … Andrew Waterman6

Feb 16

Definitionally, F_Zdinx is an invalid combination, because Zdinx requires Zfinx, the latter of which

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Definitionally, F_Zdinx is an invalid combination, because Zdinx requires Zfinx, the latter of which

Feb 16

Stephano Cetola

Jan 25

Public review for Non-ISA Specification: E-Trace

We are delighted to announce the start of the public review period for Efficient Trace for RISC-V (E-

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Public review for Non-ISA Specification: E-Trace

We are delighted to announce the start of the public review period for Efficient Trace for RISC-V (E-

Jan 25

Mark Manning, … Bruce Hoult24

Jan 25

possible to determin what extensions are available at run time?

On Wed, Jan 26, 2022 at 3:54 AM Mark Manning <mmanning@int-bio.com> wrote: This is a

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possible to determin what extensions are available at run time?

On Wed, Jan 26, 2022 at 3:54 AM Mark Manning <mmanning@int-bio.com> wrote: This is a

Jan 25

Mark Manning, … Neel Gala4

Jan 25

Why does the RISC-V ISA documentation *NOT* show encoding?

The riscv-opcodes repo : https://github.com/riscv/riscv-opcodes is also where the encodings could be

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Why does the RISC-V ISA documentation *NOT* show encoding?

The riscv-opcodes repo : https://github.com/riscv/riscv-opcodes is also where the encodings could be

Jan 25

Mark Manning, … Philipp Tomsich7

Jan 20

Think I have found a problem with the RISC V Spec 2.0

ty to all of you, io did not make the connection between fence and memory ordering instructions

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Think I have found a problem with the RISC V Spec 2.0

ty to all of you, io did not make the connection between fence and memory ordering instructions

Jan 20

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