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RISC-V ISA Dev
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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.
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Michael Zoran
, …
Tommy Murphy
9
Jan 28
Processors that implement Svpbmt
As far as I know, it doesn't. The in development Hifive Pro from sifive apparently does. On
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Processors that implement Svpbmt
As far as I know, it doesn't. The in development Hifive Pro from sifive apparently does. On
Jan 28
Kokolakis, Georgios
, …
Allen Baum
4
Jan 26
timeline for "PMP Enhancements for memory access and execution prevention on Machine mode"
This is a ratified *extension*, and that means it is official, regardless of whether it is currently
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timeline for "PMP Enhancements for memory access and execution prevention on Machine mode"
This is a ratified *extension*, and that means it is official, regardless of whether it is currently
Jan 26
Krste Asanovic
Jan 24
Public review for Zvfh/Zvfhmin
We are delighted to announce the start of the public review period for the following proposed
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Public review for Zvfh/Zvfhmin
We are delighted to announce the start of the public review period for the following proposed
Jan 24
akhilesh Kotwaliwale
, …
Tommy Murphy
16
Jan 17
RV32E toolchain
Yes i did. And I have icarus verilog version 10.1 On Tuesday, 17 January 2023 at 15:23:42 UTC+5:30
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RV32E toolchain
Yes i did. And I have icarus verilog version 10.1 On Tuesday, 17 January 2023 at 15:23:42 UTC+5:30
Jan 17
Robert Lipe
, …
Tommy Murphy
12
Jan 16
Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 5 updates in 1 topic
On Mon, Jan 16, 2023 at 4:09 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Thanks for the
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Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 5 updates in 1 topic
On Mon, Jan 16, 2023 at 4:09 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Thanks for the
Jan 16
Jan Oleksiewicz
Jan 8
XTightlyCoupledIO
Hi isa-dev Recently I have made a new custom extension providing avr8/PRU like IO instructions. https
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XTightlyCoupledIO
Hi isa-dev Recently I have made a new custom extension providing avr8/PRU like IO instructions. https
Jan 8
Ruslan Nikolaev
, …
MitchAlsup
11
Jan 5
128-bit CAS for RISC V
On Thursday, January 5, 2023 at 3:18:12 AM UTC-6 acahalan wrote: On 1/4/23, 'MitchAlsup' via
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128-bit CAS for RISC V
On Thursday, January 5, 2023 at 3:18:12 AM UTC-6 acahalan wrote: On 1/4/23, 'MitchAlsup' via
Jan 5
Olof Kindgren
, …
Robert Lipe
21
Jan 5
Thoughts on a Zrfinram extension
On Thu, Jan 5, 2023 at 8:28 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Apologies if
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Thoughts on a Zrfinram extension
On Thu, Jan 5, 2023 at 8:28 AM Tommy Murphy <tommy_...@hotmail.com> wrote: Apologies if
Jan 5
Amr Zaky
, …
Rishiyur Nikhil
3
12/27/22
Formal Spec for RISC V
Yes, there is a formal spec for the Unprivileged RV32/64 IMAFDC and Privileged RISC-V ISAs. The spec
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Formal Spec for RISC V
Yes, there is a formal spec for the Unprivileged RV32/64 IMAFDC and Privileged RISC-V ISAs. The spec
12/27/22
Simon Walker
, …
John Ingalls
10
11/30/22
Mistake in the specification?
The CBO.PREFETCH instruction does what you ask. https://raw.githubusercontent.com/riscv/riscv-CMOs/
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Mistake in the specification?
The CBO.PREFETCH instruction does what you ask. https://raw.githubusercontent.com/riscv/riscv-CMOs/
11/30/22
James Kenney
,
Andrew Waterman
4
11/18/22
Sstc Extension Issues
Note that I'm not the author of this specification. I suggest raising this question on the tech-
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Sstc Extension Issues
Note that I'm not the author of this specification. I suggest raising this question on the tech-
11/18/22
Earl Killian
, …
Tommy Murphy
4
11/9/22
Public review for standard extensions
> The review period begins today, November 8, 2022, and ends on December 23, 2002 (inclusive).
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Public review for standard extensions
> The review period begins today, November 8, 2022, and ends on December 23, 2002 (inclusive).
11/9/22
John Hauser
11/8/22
Public review for ISA/Non-ISA RISC-V Advanced Interrupt Architecture
We are delighted to announce the start of the public review period for the RISC-V Advanced Interrupt
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Public review for ISA/Non-ISA RISC-V Advanced Interrupt Architecture
We are delighted to announce the start of the public review period for the RISC-V Advanced Interrupt
11/8/22
Robert Lipe
, …
kr...@sifive.com
3
11/7/22
Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 2 updates in 1 topic
P and V are quite different. P cannot scale up to V space, and V cannot scale all the way down to P
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Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 2 updates in 1 topic
P and V are quite different. P cannot scale up to V space, and V cannot scale all the way down to P
11/7/22
Prashant Raigar
, …
Tommy Murphy
8
11/7/22
Error: unrecognized opcode `int SYSVEC'
As ever with these sorts of questions, a small, self-contained, reproducible test case would help
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Error: unrecognized opcode `int SYSVEC'
As ever with these sorts of questions, a small, self-contained, reproducible test case would help
11/7/22
Anonymous Anonymous
,
Tommy Murphy
2
11/6/22
Is P-extension dying or abandoned ?
https://lists.riscv.org/g/tech-p-ext
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Is P-extension dying or abandoned ?
https://lists.riscv.org/g/tech-p-ext
11/6/22
Aaron Durbin
, …
Abner Chang
24
10/29/22
Public review for Non-ISA Specification: RISC-V Platform-Level Interrupt Controller
RC5 released. https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0_rc5 Regards, Abner Abner
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Public review for Non-ISA Specification: RISC-V Platform-Level Interrupt Controller
RC5 released. https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0_rc5 Regards, Abner Abner
10/29/22
Krste Asanovic
10/25/22
Public Review for RISC-V Profiles RVI20, RVA20, RVA22
We are delighted to announce the start of the public review period for the RISC-V Profiles RVI20,
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Public Review for RISC-V Profiles RVI20, RVA20, RVA22
We are delighted to announce the start of the public review period for the RISC-V Profiles RVI20,
10/25/22
L Peter Deutsch
, …
BGB
12
10/20/22
[isa-dev] P.S. re: Zcmp vs expanded Zcmt
On 10/20/2022 1:23 PM, 'Mark Hill' via RISC-V ISA Dev wrote: > Hi BGB, > > The code
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[isa-dev] P.S. re: Zcmp vs expanded Zcmt
On 10/20/2022 1:23 PM, 'Mark Hill' via RISC-V ISA Dev wrote: > Hi BGB, > > The code
10/20/22
L Peter Deutsch
10/18/22
[isa-dev] Zcmp vs expanded Zcmt
How important is execution speed, as opposed to code compression? If execution speed is not a
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[isa-dev] Zcmp vs expanded Zcmt
How important is execution speed, as opposed to code compression? If execution speed is not a
10/18/22
L Peter Deutsch
, …
kr...@sifive.com
24
10/17/22
Comments on Zc* proposal (v1.0.0-RC5.7)
>>>>> On Sat, 15 Oct 2022 16:10:51 +1300, Paul Campbell <tan...@gmail.com> said
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Comments on Zc* proposal (v1.0.0-RC5.7)
>>>>> On Sat, 15 Oct 2022 16:10:51 +1300, Paul Campbell <tan...@gmail.com> said
10/17/22
Tariq Kurd
10/12/22
Public review for standard extensions Zc including Zca, Zcf, Zcd, Zcb, Zcmp, Zcmt
We are delighted to announce the start of the public review period for the following proposed
unread,
Public review for standard extensions Zc including Zca, Zcf, Zcd, Zcb, Zcmp, Zcmt
We are delighted to announce the start of the public review period for the following proposed
10/12/22
Indumathi Raju
,
Tommy Murphy
2
9/27/22
LTP configuration
> Which are the required kernel configurations to execute LTP tests? Required by what/whom?
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LTP configuration
> Which are the required kernel configurations to execute LTP tests? Required by what/whom?
9/27/22
Shubham Roy
,
Bruce Hoult
3
9/15/22
any help in understanding FESVR and HTIF
First of all thanks for the response it gave me a overview of what's happening, and linking the
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any help in understanding FESVR and HTIF
First of all thanks for the response it gave me a overview of what's happening, and linking the
9/15/22
martin ribelotta
8/31/22
FDPIC status
I'm not sure if this is the correct place to ask my question... Do any people here know the
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FDPIC status
I'm not sure if this is the correct place to ask my question... Do any people here know the
8/31/22
Robert Lipe
, …
Jan Gray
7
8/28/22
Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 1 update in 1 topic
| On Mon, Aug 29, 2022 at 12:06 PM <kr...@sifive.com> wrote: | The use case is small
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Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 1 update in 1 topic
| On Mon, Aug 29, 2022 at 12:06 PM <kr...@sifive.com> wrote: | The use case is small
8/28/22
Anthony Coulter
,
Paul A. Clayton
2
8/27/22
Rationale for {m,h,s}envcfg registers in Zicboz extension
Oops. I had intended to reply to the group. Here is the message: Forcing a cache line writeback can
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Rationale for {m,h,s}envcfg registers in Zicboz extension
Oops. I had intended to reply to the group. Here is the message: Forcing a cache line writeback can
8/27/22
Stephano Cetola
8/22/22
Public review for the Base ISAs - RV32E & RV64E
Many of you are already familiar with the two reduced bases RV32E and RV64E. The RV32E base had been
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Public review for the Base ISAs - RV32E & RV64E
Many of you are already familiar with the two reduced bases RV32E and RV64E. The RV32E base had been
8/22/22
Earl Killian
8/19/22
Public review for standard extensions Ztso
We are delighted to announce the start of the public review period for the following proposed
unread,
Public review for standard extensions Ztso
We are delighted to announce the start of the public review period for the following proposed
8/19/22
ariyosko
, …
BGB
4
8/12/22
Hi. Regarding RISC-V Exceptions, Traps, interrupts and CSRs
On 8/12/2022 10:28 AM, ariyosko wrote: > Hi. > > I am very new to RISC-V and trying to write
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Hi. Regarding RISC-V Exceptions, Traps, interrupts and CSRs
On 8/12/2022 10:28 AM, ariyosko wrote: > Hi. > > I am very new to RISC-V and trying to write
8/12/22