RISC-V ISA Dev

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Welcome to the RISC-V ISA Dev list / group. This list is used to share RISC-V ISA Development related ideas, questions and updates within the RISC-V community.

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L Peter Deutsch, BGB2

Dec 3

Compiler impact of RVA20/22/23U64 adoption

On 12/3/2024 12:27 PM, L Peter Deutsch wrote: > I'm writing a compiler one of whose targets is

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Compiler impact of RVA20/22/23U64 adoption

On 12/3/2024 12:27 PM, L Peter Deutsch wrote: > I'm writing a compiler one of whose targets is

Dec 3

Christian Herber, … BGB9

Nov 17

Public review for standard extensions Zilsd & Zclsd

On 11/17/2024 8:35 AM, Torbjørn Viem Ness wrote: > > Maybe it might make sense to define an

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Public review for standard extensions Zilsd & Zclsd

On 11/17/2024 8:35 AM, Torbjørn Viem Ness wrote: > > Maybe it might make sense to define an

Nov 17

Nov 17

How to skip Vector extension (v) when building riscv-tests?

Hi, experts: I did not include Vector extension (v) when building my RISC-V GNU toolchain; the ISA is

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How to skip Vector extension (v) when building riscv-tests?

Hi, experts: I did not include Vector extension (v) when building my RISC-V GNU toolchain; the ISA is

Nov 17

Ved Shanbhogue2

Nov 15

Public Review of the RISC-V Server SoC Specification

Greetings ! The review period for this specification is extended to conclude on 12/10/2024. regards

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Public Review of the RISC-V Server SoC Specification

Greetings ! The review period for this specification is extended to conclude on 12/10/2024. regards

Nov 15

Robert Finch, … BGB7

Nov 8

Architecture CALL / RETURN instructions

On 11/8/2024 11:40 AM, Robert Lipe wrote: > Since this is inherently quite specific to your

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Architecture CALL / RETURN instructions

On 11/8/2024 11:40 AM, Robert Lipe wrote: > Since this is inherently quite specific to your

Nov 8

Kito Cheng, … Kito Cheng5

Nov 7

Public review for Non-ISA Specification: RISC-V vector intrinsic

Hi BGB: Thanks so much for your detailed response! Let me address your points one by one: - Why are

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Public review for Non-ISA Specification: RISC-V vector intrinsic

Hi BGB: Thanks so much for your detailed response! Let me address your points one by one: - Why are

Nov 7

Anup Patel, … kr...@sifive.com13

Oct 14

Re: Comment on: RISC-V Semihosting specification

I was reacting to Bruce's suggestion to add a new ebreak. I agree it would be useful to add a

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Re: Comment on: RISC-V Semihosting specification

I was reacting to Bruce's suggestion to add a new ebreak. I agree it would be useful to add a

Oct 14

Nasir Abbas, … Al Martin4

Oct 9

FPU implementation

Based on personal experience, you should be able to get close to your goals using HardFloat as your

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FPU implementation

Based on personal experience, you should be able to get close to your goals using HardFloat as your

Oct 9

Nasir Abbas, … Bruce Hoult3

Oct 7

It uses 4 cycles per instruction, so clearly not. On Tue, Oct 8, 2024 at 5:30 AM Nasir Abbas <

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It uses 4 cycles per instruction, so clearly not. On Tue, Oct 8, 2024 at 5:30 AM Nasir Abbas <

Oct 7

Oct 7

RVA23/RVB23 public review feedback and responses

Public review has closed on the RVA23 and RVB23 profiles. The following were the primary issues

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RVA23/RVB23 public review feedback and responses

Public review has closed on the RVA23 and RVB23 profiles. The following were the primary issues

Oct 7

Nasir Abbas, Tommy Murphy2

Oct 7

Duplicate post? > Hi everyone can someone tell me that the PicoRV-32 core is pipelined. I don'

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Duplicate post? > Hi everyone can someone tell me that the PicoRV-32 core is pipelined. I don'

Oct 7

Oct 4

Summary of Privileged Architecture version 1.13 public review feedback

Public review of "Priv 1.13" - namely the Machine-Level ISA version 1.13 (aka Sm1p13) and

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Summary of Privileged Architecture version 1.13 public review feedback

Public review of "Priv 1.13" - namely the Machine-Level ISA version 1.13 (aka Sm1p13) and

Oct 4

BGB, … L Peter Deutsch25

Oct 2

Misc Idea: Mostly backwards compatible large-immediate encoding extension.

On 10/2/2024 10:01 AM, L Peter Deutsch wrote: >> If JIT, are you using the RISC-V ABI, or

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Misc Idea: Mostly backwards compatible large-immediate encoding extension.

On 10/2/2024 10:01 AM, L Peter Deutsch wrote: >> If JIT, are you using the RISC-V ABI, or

Oct 2

Robert Lipe, … BGB10

Oct 1

Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 6 updates in 1 topic

On 9/30/2024 9:13 PM, Bruce Hoult wrote: > On Sun, Sep 29, 2024 at 9:31 PM Robert Lipe <

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Re: [isa-dev] Digest for isa-dev@groups.riscv.org - 6 updates in 1 topic

On 9/30/2024 9:13 PM, Bruce Hoult wrote: > On Sun, Sep 29, 2024 at 9:31 PM Robert Lipe <

Oct 1

Muhammad Jan, … Stefan Wallentowitz4

Oct 1

RISCV VS Code debugger

Hi, if its for learning purposes, we maintain a standalone vscode plugin that is based on the Venus

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RISCV VS Code debugger

Hi, if its for learning purposes, we maintain a standalone vscode plugin that is based on the Venus

Oct 1

Sep 30

Reworked Idea: More conservative large-immediate extension.

So, I have decided to significantly scale-back the scope of my previous idea (to a more minor

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Reworked Idea: More conservative large-immediate extension.

So, I have decided to significantly scale-back the scope of my previous idea (to a more minor

Sep 30

Daren Lee, L Peter Deutsch2

Sep 30

Thoughts on GhostWrite and Architectural Implications

My opinion: GhostWrite is not an architectural issue: it is simply the result of an implementation

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Thoughts on GhostWrite and Architectural Implications

My opinion: GhostWrite is not an architectural issue: it is simply the result of an implementation

Sep 30

Sep 25

Subject: Public review for RISC-V Semihosting specification

Hi All, We are delighted to announce the start of the public review period for the proposed RISC-V

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Subject: Public review for RISC-V Semihosting specification

Hi All, We are delighted to announce the start of the public review period for the proposed RISC-V

Sep 25

Sep 4

Public Review Start - RVA23 and RVB23 Profiles

On behalf of the Chairs of the RVA23/RVB23 Profiles Task Group, we are thrilled to announce the start

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Public Review Start - RVA23 and RVB23 Profiles

On behalf of the Chairs of the RVA23/RVB23 Profiles Task Group, we are thrilled to announce the start

Sep 4

Jacob Bachmeyer, … 唐盛銘3

Sep 3

May I ask the definition of faulting instruction, especially in a scenario that a 32-bit machine with

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May I ask the definition of faulting instruction, especially in a scenario that a 32-bit machine with

Sep 3

Sep 3

Priv 1.13 public review announcement

The Chair and Vice-Chair of the Privileged ISA Committee are pleased to announce the start of the

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Priv 1.13 public review announcement

The Chair and Vice-Chair of the Privileged ISA Committee are pleased to announce the start of the

Sep 3

Amr Zaky, … Rishiyur Nikhil7

Aug 30

Capturing RISC V instructions

Or, instead of Spike, you could build and run the official formal specification for the RISC-V ISA:

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Capturing RISC V instructions

Or, instead of Spike, you could build and run the official formal specification for the RISC-V ISA:

Aug 30

Peter Ashenden, Andrew Waterman2

Aug 29

Clarification of Zcb dependencies

The second option. I think this sentence in the intro makes it clear: https://github.com/riscv/riscv-

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Clarification of Zcb dependencies

The second option. I think this sentence in the intro makes it clear: https://github.com/riscv/riscv-

Aug 29

Aug 23

Re: [RISC-V tech-announce] Public review for Smctr/Ssctr ISA extensions

The public review period for Smctr/Ssctr has closed. I received two requests for clarifications:

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Re: [RISC-V tech-announce] Public review for Smctr/Ssctr ISA extensions

The public review period for Smctr/Ssctr has closed. I received two requests for clarifications:

Aug 23

Aug 14

Public Review | RISC-V N-Trace, RISC-V Trace Control Interface and RISC-V Trace Connectors

On behalf of the Chair and Vice-Chair of the N-Trace Task Group, we are delighted to announce the

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Public Review | RISC-V N-Trace, RISC-V Trace Control Interface and RISC-V Trace Connectors

On behalf of the Chair and Vice-Chair of the N-Trace Task Group, we are delighted to announce the

Aug 14

Guy Lemieux, Tommy Murphy2

Aug 4

Informal / unofficial survey of RISC-V processor development

In case it helps at all, there's a good list of RISC-V based MCUs/development boards here: https:

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Informal / unofficial survey of RISC-V processor development

In case it helps at all, there's a good list of RISC-V based MCUs/development boards here: https:

Aug 4

Jul 28

Re: [isa-dev] Need Help Understanding RISC-V A Extension Instructions and Their Use Cases

On Sun, Jul 28, 2024 at 03:28:46AM -0700, Hiruna Vishwamith wrote: >I have been studying the '

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Re: [isa-dev] Need Help Understanding RISC-V A Extension Instructions and Their Use Cases

On Sun, Jul 28, 2024 at 03:28:46AM -0700, Hiruna Vishwamith wrote: >I have been studying the '

Jul 28

Jul 28

Does the glibc coroutine library utilize the feature of returning stack to support coroutines?

I have attempted to use glibc's coroutine-related library functions, and from the disassembled

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Does the glibc coroutine library utilize the feature of returning stack to support coroutines?

I have attempted to use glibc's coroutine-related library functions, and from the disassembled

Jul 28

Jul 23

Public review for Smctr/Ssctr ISA extensions

We are delighted to announce the start of the public review period for the proposed Control Transfer

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Public review for Smctr/Ssctr ISA extensions

We are delighted to announce the start of the public review period for the proposed Control Transfer

Jul 23

Boul chandra Garai

Jul 23

Assistance Required for executing the targeted workload on spike RISC-V ISA after adding custom trigonometric Instructions

Hello Team, I hope this message finds you well. I am seeking assistance with adding new instructions

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Assistance Required for executing the targeted workload on spike RISC-V ISA after adding custom trigonometric Instructions

Hello Team, I hope this message finds you well. I am seeking assistance with adding new instructions

Jul 23

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