I have a RAM that is internally multi-banked -- in that it has 1 TL node through which it can accept multiple requests sequentially, hold them until serviced, and respond in the D channel as and when the internal banks respond to different requests (via an arbiter).
However, changing sourceIds mid-flight is prohibited (according to an assert in tilelink/Monitor.scala: function legalizeMultibeatD). Could someone kindly explain the reasoning behind having this restriction?
If, towards a special case, we can guarantee that different requests (with different sourceIds) that arrive at TL node of the RAM are from distinct client nodes, can this restriction then be somehow circumvented?
Thanks in advance, and a happy new year,