Interrupt and exception handling

[sajjad ahmed]

Hello everyone.

i want to implement interrupt and exception handling in my design but confused about the handler. like how we handle an exception in hardware. for example i have an exception of load address misaligned. i have raised the exception flag and i know the csr mapping on exceptions but what will be the operation of handling this exception. whether i have to jump to a handler code or i will have some logic circuit for handling this. same thing goes for interrupts.

please guide me.

your support is always appreciated.

 

[Kelvin Goveas]

Please read sections 3.1.7, 3.1.8 and 3.1.9 of the RISC V privileged spec for the architectural handling of traps and interrupts. You can then decide on your micro-architectural implementation. The net effect is the core would transition to executing code in an exception handler at a virtual address which is a function of m[s]tvec, m[s]edeleg/m[s]ideleg and update m[s]cause and m[s]epc. The latest spec can be found at following link:

https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20200911-e869081

Kelvin