How to generate Verilog file for Icache of Rocketchip?

32 views

Skip to first unread message

Otrera Quinn

unread,

Nov 25, 2024, 7:41:12 AM11/25/24

to RISC-V HW Dev

I am working on the instruction cache of rocket chip as a part of my project, but I am not able to figure out how will test only the icache and generate it's Verilog code.I am using IntelliJ ide on MacOS

Reply all

Reply to author

Forward

0 new messages