Regarding AXI slave error.

[saravanan]

Hi ,

I am trying to Read from MMIO mapped slave region from RISCV. Slave
response with slave error. But RISCV hangs in read.

In this do Mcause register has to be updated with Load access fault ? 
Or could please let me know, how to firmware handle this issue ?

Thanks

Saravanan


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[Megan Wachs]

This is not  RISC-V architectural issue, this will depend on what implementation you are actually using. So you need to provide more information about the RISC-V implementation you're using (Spike? Rocket-Chip? a specific FPGA?), what memory region you're accessing, and what you expect to happen.

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[saravanan]

Hi Megan,

1. We are using rocketchip.

2. I am trying to access axi slave which is mapped in MMIO space. As we are accesing the slave without configuring it it return axi slave error. This is expected behavior.

3. My assumption  is

           i. During write, if we get slave error, then store access fault should be set in mcause register.

           ii. During read, if we get slave error, then Load access fault should be set in mcause register.

           Do my assumption is right ?

Thanks

Saravanan