Implementation of atomic instructions using LR/SC pair

[Sreenadh S]

In our rv64imafd multi-core  implementation, we had implemented Atomic instructions as a combination of lr and  sc instruction. Is
this implementation complaint to the risc-v specification? Will it make any
issues when running programs compiled for riscv?
Also is there any chance of following type of assembly code generated by the compiler:

lr.d x11, 0(X5)
amoadd.d X2, 0(X6)
sc.d X7, 0(x5)
[In our implementation the above sc.d will always fail]

[Dan Petrisko]

I can't speak to the general compiler case, but our rv64imafd multicore used to emulate AMO using LR/SC pairs and we were able to boot full SMP Linux (and all multicore benchmarks we tried). We wrote https://github.com/black-parrot-sdk/perch/blob/master/atomics.S for the routines if it's of interest to you.

Best,

Dan

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