Memory map on RocketChip

[Pranav Shreyas]

Hello, 

I'm trying to understand the memory map of the RocketChip and having trouble understanding the generated memory map:

Which is the RAM address in the map? Is the external RAM SimAXIMem module ?  From which address do i begin to load the my hex file? Thanks!!

Interrupt map (2 harts 2 interrupts):

  [1, 2] => ExampleRocketTop

 

Gene Generated Address Map

        dmInner 0 - 1000, RWX

         ExampleRocketTop 60000000 - 80000000, RWX

         clint 2000000 - 2010000, RW

         plic c000000 - 10000000, RW

         bootrom 10000 - 20000, RX

         error 3000 - 4000, RW

         ExampleRocketTop 80000000 - 90000000, RWX [C]

         zeros_0 a000000 - c000000, RWX [C]

 

/dts-v1/;

 

/ {

         #address-cells = <1>;

         #size-cells = <1>;

         compatible = "ucbbar,rocketchip-unknown-dev";

         model = "ucbbar,rocketchip-unknown";

          L8: cpus {

                #address-cells = <1>;

                #size-cells = <0>;

                timebase-frequency = <1000000>;

                L12: cpu@0 {

                        clock-frequency = <0>;

                        compatible = "sifive,rocket0", "riscv";

                        d-cache-block-size = <64>;

                        d-cache-sets = <64>;

                        d-cache-size = <16384>;

                        d-tlb-sets = <1>;

                        d-tlb-size = <32>;

                        device_type = "cpu";

                        i-cache-block-size = <64>;

                        i-cache-sets = <64>;

                        i-cache-size = <16384>;

                        i-tlb-sets = <1>;

                        i-tlb-size = <32>;

                        mmu-type = "riscv,sv39";

                        next-level-cache = <&L2 &L5>;

                        reg = <0>;

                        riscv,isa = "rv64imafdc";

                        status = "okay";

                        tlb-split;

                        L13: interrupt-controller {

                                #interrupt-cells = <1>;

                                compatible = "riscv,cpu-intc";

                                interrupt-controller;

                        };

                };

        };

         L2: memory@80000000 {

                device_type = "memory";

                reg = <0x80000000 0x10000000>;

        };

         L7: soc {

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "ucbbar,rocketchip-unknown-soc", "simple-bus";

                ranges;

                L11: clint@2000000 {

                        compatible = "riscv,clint0";

                        interrupts-extended = <&L13 3 &L13 7>;

                        reg = <0x2000000 0x10000>;

                };

                L9: debug-controller@0 {

                        compatible = "sifive,debug-013", "riscv,debug-013";

                        interrupts-extended = <&L13 65535>;

                        reg = <0x0 0x1000>;

                };

                L1: error-device@3000 {

                        compatible = "sifive,error0";

                        reg = <0x3000 0x1000>;

                };

                L10: interrupt-controller@c000000 {

                        #address-cells = <0>;

                        #interrupt-cells = <1>;

                        compatible = "riscv,plic0";

                        interrupt-controller;

                        interrupts-extended = <&L13 11 &L13 9>;

                        reg = <0xc000000 0x4000000>;

                        riscv,ndev = <2>;

                };

                L3: mmio@60000000 {

                        reg = <0x60000000 0x20000000>;

                };

                L0: offchip-interrupts {

                        interrupt-parent = <&L10>;

                        interrupts = <1 2>;

                };

                L4: rom@10000 {

                        reg = <0x10000 0x10000>;

                };

                L5: rom@a000000 {

                        compatible = "ucbbar,cacheable-zero";

                        reg = <0xa000000 0x2000000>;

                };

         };

 R             Regards,

                 Pranav

Re

};

[Ben Keller]

Hi Pranav,

The default base address for external main memory in Rocket chip is 0x80000000; the SimAXIMem module does indeed play the role of DRAM in the provided simulation framework.

-Ben 

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[saravanan]

Hi Pranav,

ExampleRocketTop 80000000 - 90000000, RWX [C]

Above one is RAM address. In the above line [C] - represents cachable region, i believe.

In Riscv the regions other than cachable are treated as non-cachable

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