Parallel processing support (CSP not SMP) - anyone interested?

[Kevin Cameron]

HI All,

Communicating Sequential Processes is a software methodology in which code describes FSMs that communicate by message-passing rather than shared memory. It was supported on the Transputer - a RISC-like processor made by Inmos in the 1980s.

Some of the message passing approach can be inferred in regular C/C++ code such that SMP code can be converted to CSP style for a more scalable approach to massively parallel computing. Doing that efficiently requires some hardware extensions on a regular processor.

Please let me know if you are interested in extending RISC-V to support the CSP paradigm, manycore (large arrays of simple cores), or PiM.

Regards,
Kev.

[Samuel Falvo II]

On Wed, Jan 11, 2017 at 5:32 PM, Kevin Cameron <camer...@gmail.com> wrote:
> Communicating Sequential Processes is a software methodology in which code
> describes FSMs that communicate by message-passing rather than shared
> memory. It was supported on the Transputer - a RISC-like processor made by
> Inmos in the 1980s.

I'd love to see SpaceWire and IEEE-1355 make a come-back! It'd map
*perfectly* onto Pmod ports found on a lot of FPGA boards today. It'd
be a far better fit for many kinds of I/O than SPI would, as it'd
truly support asynchronous operation between communicating endpoints.

> Please let me know if you are interested in extending RISC-V to support the
> CSP paradigm, manycore (large arrays of simple cores), or PiM.

I have an interest in this, not just for massive compute ability, but
also just for I/O in general. I have experience with the GreenArrays
144-core Forth chip, and even more with its direct ancestor, the
Intellasys SeaForth-24 core chip. It's a lot of fun to bit-bang VGA
at-speed when your individual cores are able to run at 500MHz and
communicate with each other via messaging on a near-zero-latency
channel.

--
Samuel A. Falvo II

[Sean Halle]

Here's a programming model for CSP that drops in to C.  You just link to the library and then make calls to create CSP processes, and then send and receive communications between them.  It's 8x lower overhead than linux pthreads on single-chip machines, and up to 100x lower overhead on multi-socket servers.  It's much easier to reason about and get correct code, while being faster than pthreads.

http://opensourceresearchinstitute.org/pmwiki.php/SSR/HomePage

This rides on top of protoruntime, 

http://opensourceresearchinstitute.org/pmwiki.php/PRT/HomePage

It's a toolkit for creating synchronization commands, which we will be supporting in hardware in our upcoming high performance RISC-V core.  On that processor, this version of CSP will have synchronization overhead on the order of a dozen instructions -- compared to tens of thousands of instructions of overhead for the current best pthreads. 

To play with it, the code is a bit out of date, but if there is any interest I will update to a debian package that will install everything, and provide hello world examples of usage.

Best,

Sean

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[Kevin Cameron]

I have a language in mind, my extended C++ -

  http://parallel.cc

I'm hoping I can leverage LLVM for that.

However, some of the extensions I'm looking for are less about CSP, and more about handling legacy code issues, and should be fairly language independent.

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[Samuel Falvo II]

On Wed, Jan 11, 2017 at 9:46 PM, Kevin Cameron <camer...@gmail.com> wrote:
> I have a language in mind, my extended C++ -
>
> http://parallel.cc
>
> I'm hoping I can leverage LLVM for that.

There's also Rust, which similarly targets LLVM.

[Wink Saville]

I'm very interested!

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[Dr. Chandan Haldar]

We at Morphing Machines would be very interested as well.  Have a look at http://morphing.in/redefine.  There is an introductory video that might be helpful as a quick overview.  REDEFINE was presented at the 4th RISC-V Workshop last year in the poster session.  REDEFINE is a reconfigurable massively parallel processor with a message-passing architecture with a high-speed NoC and a subset of the 32-bit RISC-V ISA as the internal ISA of each processing element.  Developed entirely in Chisel, our 256-core config is working nicely on a Virtex-7 FPGA ensemble.  Our base compiler (LLVM derivative) compiles plain C programs to target REDEFINE via an OpenCL-like API.  A CSP-like programming model for REDEFINE and evolution of a mature compiler framework is of great interest to us and to our customers.  Currently our focus is on integrating REDEFINE with a full-fledged 64-bit multi-core RISC-V processor on the same SoC to make a complete standalone processor to offer a low-power alternative to GPUs, progressing towards a prototype SoC tape-out, continuing the scaling up of the REDEFINE fabric to larger configs, and moving towards a mature compiler framework.  A Rust HIR/MIR-like compilation flow for REDEFINE is an exciting possibility on my mind, but we have limited resources to pursue everything that appears exciting.  REDEFINE is not open-source as of now, but we are open to collaborations and ideas, specially on the compiler side.  We are at Bangalore in India.

Cheers.

Chandan

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[Jan Gray]

Hi Kev,

 

The work-in-progress GRVI Phalanx [http://fpga.org/grvi-phalanx] FPGA accelerator framework implements arrays of clusters of RISC-V cores. Within a cluster, optional GRVI RISC-V cores and optional accelerator cores share a multiported bank interleaved cluster shared memory (CRAM). Communication between clusters is via message passing. Currently each cluster can send/receive a 32 byte message per cycle until the NOC saturates.

 

A copy of a 1-32 B message in CRAM can be sent across the NOC by software by means of a memory-mapped I/O store to the cluster’s NOC interface controller (“NOC ITF” in Fig. 2 in this paper: [http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf]). For Phalanx this is the basic message passing primitive. Then there is a whole design space of possible ways to extend RISC-V to enable different parallel programming models, features, and semantics, including different kinds of message passing. It is exciting to see the start of a discussion about programming models, languages, and infrastructure they might require – runtimes and hardware assist.

 

FYI last month a 30 x 7 cluster x 8 core = a 1680 core + 26 MB SRAM GRVI Phalanx, targeting a Xilinx XCVU9P, booted and ran correctly. [http://fpga.org/2017/01/12/grvi-phalanx-joins-the-kilocore-club/]

 

Cheers,

Jan Gray

Gray Research LLC

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