LR/SC: Multi-Core Implementation in Rocket

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Mar 5, 2021, 12:19:17 PMMar 5
to RISC-V HW Dev

I'm studying the source code of Rocket-chip, interested in the implementation of the reservation set for LR/SC mentioned in the spec. Unfortunately, I only found the reservation set register exists in local D$ (NBDCache.scala, DCache.scala). I didn't found ports for interactions between different harts.

I'm eager to know the mechanism for a hart to observe the store to the registered address from other hart, and how it is implemented in Rocket or Boom.

Thanks a lot!

Andrew Waterman

Mar 5, 2021, 5:57:20 PMMar 5
to 胡博涵, RISC-V HW Dev
The coherence protocol between the cores’ caches is responsible for the inter-core interactions. (And there’s only one hart per core.) So the D$ code contains all of the details.


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